PIEZOELECTRIC TRANSDUCER DRIVER CIRCUIT WITH ADJUSTABLE OUTPUT LEVEL

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IP.com Disclosure Number: IPCOM000006724D
Publication Date: 01-Dec-1992
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Publishing Venue

Motorola Technical Bulletins

Related People

Gary Pace - Author

Abstract

In some battery powered products using a piezo- electric transducer as an alerting device, it is desirable to be able to control the alert tone loudness. In addition, it is sometimes desirable to reduce the current drain drawn from the battery by the piezoelectric transducer driver circuit, particularly when the battery approaches an end- of-life condition and battery life must be prolonged. The piezoelectric transducer driver circuit shown in Figure 1 provides the capability to adjust the transducer sound pressure level (SPL) as well as control the current drawn from the battery.

Copyright

Motorola Inc. December 1992

Language

English (United States)

Country

United States

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2 pages / 134.9 KB

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MOTOROLA INC. Technical Developments Volume 17 December 1992

PIEZOELECTRIC TRANSDUCER DRIVER CIRCUIT WITH ADJUSTABLE OUTPUT LEVEL

by Gary Pace

  In some battery powered products using a piezo- electric transducer as an alerting device, it is desirable to be able to control the alert tone loudness. In addition, it is sometimes desirable to reduce the current drain drawn from the battery by the piezoelectric transducer driver circuit, particularly when the battery approaches an end- of-life condition and battery life must be prolonged. The piezoelectric transducer driver circuit shown in Figure 1 provides the capability to adjust the transducer sound pressure level (SPL) as well as control the current drawn from the battery.

  During operation of the circuit in Figure 1, a square wave input signal (typically 3200Hz) is applied to the input "IN". The output drive level at output "OUT2" to the piezoelectric transducer can be selected to be of one of two levels by setting input "SPL" to a HIGH("1") or a LOW("0"). Assuming that input "SPL" has been set LOW, which turns transistor Q14 ON and disables cur- rent mirror QlUQ12, the higher level will be provided at output "OUT2". During the high interval of the input signal, current mirror transistor Q9 provides 4 current source outputs. Two of these output currents(I2,14) are applied to a bistable circuit consisting of transistors Q3 through Q7. The other two output currents from tran- sistor Q9(I5&) are applied to transistors Qll,Ql2,Q14 and Q15 which form a control circuit for adjusting the switching threshold of the bistable circuit. At the begin- ning of the high level portion of the input signal, transis- tor 413 is turned OFF, current mirror Q6/Q7 is deactivated resulting in the bistable circuit powering up in an ON state in which transistors Q3,Q4 and QS arc conducting. Transistor QlO is biased by the input inter- face circuit to prevent collector-emitter voltage satura- tion in transistor Q4. After approximately a 1OuS delay provided by the delay circuit, transistor Q13 is turned ON, activating current mirror Q6/Q7. The delay circuit ensures that switching transistors Ql and Q2 are turned ON following the leading edge of each high interval of the input signal applied at the "IN" input. Transistors Ql and Q2 are turned ON by taking the output current from transistor Q5 in the bistable circuit and using cur- rent mirror transistor Q8 to apply current to the two

154

base drive circuits.

  An inductor current limiting circuit is realized by using the bistable circuit, a double emitter device for Ql and resistor Rl. The peak current in inductor L is deter- mined by the ratio of the two emitter areas of transistor Ql, the value of Rl, the ratio of the emitter areas of transistors Q3 and 44, the ratio of bias currents I1 and 12, and the ratio of the emitter areas of transistors Q 11 and Q12 when current mirror Ql l/Q12 is enabled. For the parameter values given in Figure 1, the peak current...

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