The IP.com Prior Art Database
English (United States)
2 pages / 63.5 KB
Method for reducing nonuniformity in SOI stacks and related substrates
Disclosed is a method for reducing nonuniformity in silicon on insulator (SOI) stacks and related substrates. Benefits include improved reliability.
SOI wafers are conventionally produced by directly polishing SOI Si films. However, the process produces nonuniform results. This problem is conventionally solved by parallel ion bombardment and planarization.
The disclosed method reduces nonuniformity in SOI stacks and related substrates. The main components of the disclosed method include:
• Incorporating deposition of a sacrificial material atop a nonuniform SOI substrate
• Planarization until high points of the SOI stack are exposed
• Selective wet etch deeper than the valley-filling sacrificial film to yield a highly uniform SOI substrate for depleted substrate transisitor (DST) devices
The key elements of the disclosed method include:
- Deposition of the sacrificial film that mimics the contour of the SOI stack, which requires increased uniformity
- Planarization/polish of the film, end-pointing when high points of underlying film are exposed
- Application of a wet etch that isotropically dissolves the SOI layer and is highly selective to the sacrificial valley-filling film
- Wet etch that is conducted beyond depth of sacrificial film, yielding a highly uniform SOI stack
and aids the reduction of both the local and global nonuniformity in the wafer
- Scope of the disclosed method can also include uniformity improvements in germanium on insulator (GOI) and strained (SiGe) substrates
The disclosed method provides advantages, including:...