Critical Path Determination

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IP.com Disclosure Number: IPCOM000047896D
Publication Date: 01-Dec-1983
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IBM Technical Disclosure Bulletin (TDB 12-83 p.3730-3732)

Related People

Reiter, MR - Author [+1] [-1]
Poughkeepsie
Tryon, DR - Author
Poughkeepsie

Abstract

A determination of the number of critical paths in a processor, where a critical path is defined as one that cycle-limits the processor, is important in evaluating system failure risk. System failure risk is defined to be the probability that the processor will not run at cycle time even though each path has been timed to a high confidence level by verification programs. Clearly, even though each path has been timed, the probability of all paths working and consequently the processor working declines as the number of critical paths increases. Described below is a technique for determining the number of critical paths in a processor. The following terms are used: block - a representation of a circuit. Several blocks may be used to model one circuit. path - a series of blocks between SRLs.

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English (United States)

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Critical Path Determination

A determination of the number of critical paths in a processor, where a critical path is defined as one that cycle-limits the processor, is important in evaluating system failure risk. System failure risk is defined to be the probability that the processor will not run at cycle time even though each path has been timed to a high confidence level by verification programs. Clearly, even though each path has been timed, the probability of all paths working and consequently the processor working declines as the number of critical paths increases. Described below is a technique for determining the number of critical paths in a processor. The following terms are used: block - a representation of a circuit. Several blocks may be used to model one circuit. path - a series of blocks between SRLs. SAS - static analysis program to verify Boolean equivalence between two models (such as a functional and

logical model). (Reference 1) SCR - signal correspondence record which is used to define the correspondence between the two SAS

models. SRL - shift register latch. Cycle time is defined

between SRL-to-SRL boundaries.

test - a timing verification check that is performed at

a SRL (between data and clock, for example).

Several tests can be performed at the same SRL. TA - timing analysis program that predicts slack for each path in the logic. slack - a measure of whether a TA test is passed. Zero or near-zero slack is defined to be critical and

positive slack is "goodness". The technique is generally illustrated in the drawing: The TA program including associated post-processing programs provide output from which can be derived the number of blocks in a cri...

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