IBM Technical Disclosure Bulletin (TDB 04-78 p5055-5057)
Tsui, F - Author
English (United States)
2 pages / 62.9 KB
Microinstruction Sequencing Control for Fast Signal Processing
In digital signal processing, multiplications are mostly by known constants, and they can be done by successive shifts and additions in order to save the hardware expenditure of a full-fledged high-speed multiplier. It is possible to speed up the multiplications by (a) using the "canonical signed digit code" (CSDC) representation of the constants to reduce the average number of shift- and-adds needed, (b) incorporating the CSDCs directly in multiply subroutines using one microinstruction for each shift-and-add, and (c) implementing a fast microinstruction sequencing control which is to make the to-and-fro subroutine linkages without taking extra microinstruction cycles [1, 2]. Commercially available "microprogram sequencer" slices cannot be used directly for the needed sequencing control because the functions they provide are mainly "push" and "pop", and both involve a change of the stack-pointer content.
The system described herein represents a modification to such microprogram sequencers, which will then allow them to be directly
usable for the fast subroutine linkages mentioned above. In addition to known "push" and "pop" functions, where: Push means: (SP) <-- (SP) + 1, and STK new (SP) <-- (PC) (increment stack pointer, then store program-counter content in stack), Pop means: Output <-- STK (SP) , and (SP) <-- (SP)-1 (output SP-pointed stack content, then decrement stack pointer),
a third function...