Parallel Binary Adder

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IP.com Disclosure Number: IPCOM000075584D
Publication Date: 01-Oct-1971
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Publishing Venue

IBM Technical Disclosure Bulletin (TDB 10-71 p1477)

Related People

Chaudhry, MS - Author [+1] [-1]
United Kingdom
Truslove, DJ - Author
United Kingdom

Abstract

This adder uses the principle that when, at an adder stage, the partial sum and carry-in digits are both "1", a carry is propagated through to a higher stage in which the sum and carry-in digits are both "0" and the full sum digits for each stage through which the carry is propagated is 0.

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English (United States)

Country

United States

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2 pages / 42.4 KB

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Parallel Binary Adder

This adder uses the principle that when, at an adder stage, the partial sum and carry-in digits are both "1", a carry is propagated through to a higher stage in which the sum and carry-in digits are both "0" and the full sum digits for each stage through which the carry is propagated is 0.

Fig. 1 shows a four-stage adder employing the above principle. The carry propagate circuitry comprises essentially groups of AND circuits 6, 16 and 26, connected to receive sum and carry outputs from respective ones of half-adders HA1 to HA4. An output from an OR circuit 27, connected to receive outputs from the highest order group of AND circuits, is used to propagate the carry into a further group of adders. Fig. 2 shows connections between four groups of four- bit adders to form a sixteen-bit adder. The group 1 adder is as shown in Fig. 1, and the remaining adders are modified to accept a carry-in bit in the lowest order, having a carry control circuit similar to that shown between half-adders HA1 and HA2 of Fig. 1.

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