Floorplan for a Scalable NUMA System

IP.com Prior Art Database Disclosure
IP.com Disclosure Number: IPCOM000126511D
 Publication Date: 22-Jul-2005
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The IP.com Prior Art Database

Abstract

Disclosed is a method for the layout of a large-scale scalable NUMA system so that the processor network interconnect wiring density (i.e., the number of cables) is kept small and the average length and maximum length of the cables be kept short. These are among the factors that determine the scalability of the system because they determine whether the system can be scaled up to a specified number of processor nodes. These factors affect the total power consumption of the system: the more interconnect links and the longer the links in the interconnect, the higher the power consumption by the system. Longer links also affect signal latencies and therefore the overall system performance. Designing a large-scale NUMA system to these constraints is a complex task, as is evidenced by the tangle of wires that can be observed growing behind the racks of most MP systems. A system design that can achieve these goals is highly desirable. In the present invention the goal is to scale the system to thousands of processor nodes. We have provided for system scalability with an effective floorplan to minimize cable density, average cable length, and maximum cable length.

Language

English (United States)

Document File

2 pages / 112.2 KB

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Floorplan for a Scalable NUMA System

     The topology for the parallel system of the present invention is described in the figure below,

P P P

                            P P P P P

   P P P

P P

P

P P

level 1

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     The pattern is regular, hierarchical and periodic; a set of regular forms that repeat at larger scales in a recursive pattern as illustrated in the figure below,

256 proc

1K proc

4K proc

16K proc

64K proc

     The resulting pattern has a fractal geometry and has characteristics that are self-similar (same forms occur when viewed at different scales). The benefits of the type of floorplan result mostly from the self-similar nature of the topology: modular construction, larger density of the interconnect links is for the shortest wires, where the best delay, power consumption and cost can be obtained; level 1 router and links can be embedded in the processor node PC board; level 2 links can be embedded into the backplane. In the preferred configuration all routers levels 3 and higher can be built into small daughtercards that plug on to the processor node PC board and has connector connection to the backplane where cables can be connected. All boards can accept a router daughter card. There are several types of daughtercards depending on the driver capability of the router (and the length of cable that the router drives.) Notice that with this type of layout, it is fa...

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