Multiple FIFO in a Single RAM

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Multiple FIFO in a Single RAM

Idea: Naftaly Blum, IL-Hod Hasharon

In digital systems in general, and communication systems in particular, it is often required to manage a multiple of FIFO (First In First Out) memories, for example, one for every communication port. However, when such communication systems are implemented using FPGA (Field Programmable Gate-Array) components, the available memories are insufficient. In an FPGA, there would typically be a multitude of tiny RAMs (Random Access Memories), too small to handle all the FIFO memories, and one or very few very large RAMs, large enough for the FIFO requirements, but too few.

Alternative known solutions to the problem are the use of more or larger FPGA units, or to speed up the processing frequency so that tiny FIFO memories for each port would suffice. In any case, those would be much costlier solutions than the new solution.

According to the new solution, a large memory segment for several concurrent smaller FIFO memories will be used. A logic block diagram of the idea is depicted in figure 1. Each of the ingress ports is routed to a "tiny FIFO". The function of the tiny FIFO is to store information until it is transferred to the large RAM. The large RAM is divided in n segments, and each of them is allocated to a specific port. The MUX (Multiplexer) takes care to sequentially scan the "tiny FIFOs" and the transfer their contents to the large RAM, which can now be viewed as a collection of n FIFO memories, shared between the n ports.

A detailed view of how the RAM is time-shared is depicted in figure 2. There is a scan logic, which continuously scan the tiny FIFOs, and if they are not empty, transfers their contents to the allocated segment in the large RAM. There is a bank of n write pointers, each initially pointing at the start address o...