Optimized circuit structure for cascading transmission gate circuits and multiplexors (25-May-2006)
A method of connecting the drain of the first transmission gate to the gate of second transmission gate to reduce delay is shown. In order to do that, the controls that drive the source of the second transmission have to be modified to generate logically equivalent circuits.
Optimized circuit structure for cascading transmission gate circuits and multiplexors
As feature sizes of integrated circuit technologies continue to shrink, circuit techniques have to evolve as certain certain techniques useful in prior technologies can no longer be used requiring innovative approaches to achieve optimal performance. Described is an optimized circuit topology that provides a higher performing circuit at 0.065um feature sizes than traditional design approaches.
This invention rearranges transistor interconnections in a new way that allows identical function to be performed with fewer gate delays. With the more recent technologies, the drain of a transmission gate is not allowed to connect directly to the source of a 2nd transmission gate because the behavior of that type of structure is harder to model accurately. Therefore, an intermediate driving gate such as an inverter or nand gate must be used. This gate necessarily adds delay.
When cascading 2 levels of transmission gate mux, the output of the first is connected to the gate of the transistors in the 2nd stage instead of the source of the transistors. This connection does not require and intervening driving gate. The other controls the produce the function of the mux can be appropriately modified to provide the mux function.
A specific pair of circuits are contrasted here to illustrate the invention. The invention can be extended to other circuits.
Consider a 4:1 transmission gate mux feeding and 2nd stage transmission function which is integrated with other controls. The function of the 2nd stage transmission gate is given by the truth table below. The circuit is a bit-slice. The labels with (i) are intended to be unique to a specific bit of a large bus (often 16, 32 or 64 bits wide). Labels without the (i) are signals that are identical for all bits of the bus.
In this function, the output of the first mux - R(i), is passed through unchanged, or complemented depending on the settings of the c...
Find More Documents Like This
Download this Disclosure
Click here if you want to sign-in now.
