The IP.com Prior Art Database
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Loopto Improve Read Timing Margin for External Memory Interface Applications in FPGA Devices
Skew is an important factor that limited the performance of the system, especially in the high speed application, for example memory interface. Double data rate memory controller can be implemented in FPGA devices. As new DDR memory spec offered higher performance with 800Mbs to 1Gbs data rate, the timing budget left to FPGA becomes much smaller. DDR memory interface has data strobe (DQS) transmitted along with a group of data (DQ) for data capture in the receiver side. DQS is edge-aligned with data during read and center-aligned with data during write. All the skew and jitter among all the DQ in the group and DQS will be treated as uncertainty and will be subtracted from valid sampling window. So it is important to reduce skew among all DQ and DQS for both read and write.
This invention provides an innovated scheme to continuously find the skew between DQ and DQS paths and adjust the delay chain setting accordingly to compensate the skew between two paths.
Minimize the skew among all DQ and DQS path can help to improve data valide window. There are a couple of methods can be used to reduce the skew. Compensate the skew by programming the same delay chain setting for all devices or programming on-chip non-volatile elements for each individual device. This method needs to accurately measure the skew information in order to set the proper delays, which is not a trivial job. Also the process, voltage and temperature variation results in variations of the skew, which can not be compensate by fixed delay settings.
This invention continuously finds the skew between DQ and DQS paths and adjust the delay chain setting accordingly to compensate the skew between two paths.
During a read operation, FPGA will capture data using data strobe. Figure 1 shows the read path in FPGA. Data (DQ) goes through input buffer and gets to register data input. DQS goes through input buffer and a phase shift delay chain and gets to register clock. The phase shift delay chain is used to shift DQS signal to the middle of the sampling window. There are skew adjustment delay chains in both DQ path and DQS path. The skew adjustment delay chain is a variable delay chain which delay setting can be programmed or coming from Skew Locked Loop (SLL). Bypassing the phase shift delay chain we want 0 skew between DQ path and DQS path.
Figure1 DDR Memory Interface Read Path in FPGA
To continuously find the skew between DQ and DQS paths without disrupting the normal operation, a mimic DQ path and a mimic DQS path is needed. Figure 2 shows the block diagram of skew locked loop.
The SLL consisted with DQ mimic path, DQS mimic path, Phase Comparator, Counter Control Logic and two counters (DQ Counter...