Verifying Circuits With Asynchronous Interfaces During RTL Simulation (17-Oct-2006)

By

Arvind Garg

Abstract

Today’s circuit designs have multiple asynchronous clocks.  Synchronizers are used at clock domain crossings to manage the meta-stability that may arise and synchronize the launching domain's signal to the clock of the capturing domain.  Many complex synchronization scenarios may arise depending on which value (0 or 1) the synchronizer flip-flop settles after the occurrence of a violation on the flip-flop and the convergence of the outputs of such synchronizer circuits in the design.  Current verification methodologies (RTL/postlayout) do not address verification of the above-mentioned scenarios, so there are very high chances of circuits with bugs going into the silicon.  This paper presents a method that assures a complete verification of the circuit design at the RTL stage under all possible synchronization scenarios that may arise when the silicon is functioning.

Body

FIG. 1 shows a simple and widely used two stage synchronizer circuit.  As the signal from the launching clock domain(CLK1) is totally asynchronous to the first stage of the synchronizer (triggered on CLK2), there can be setup/hold violations at the first stage flop of the synchronizer (S1), and thus the output of S1 can either settle to the previous value or the new value.

                                                            (Fig. 1)

The following three cases may arise when the input of the first stage of synchronizer (S1) changes:

1) There is no violation at the first stage of the synchronizer (S1) and it correctly latches        

     the change at it's input. (Fig. 2)

2) There is a violation at the first stage of the synchronizer and it settles to the new value.

    (Same result as that of case 1). (Fig. 3)

3) There is a violation at the first stage of the synchronizer and it settles at the previous  value. (Fig. 4)

In order for the circuit to function correctly, the logic following the synchronizer (L1) should be able to handle all of the above conditions.

                 CLK2

                 A1

                 S1  

                 S2

                                                            (Fig. 2)

                 CLK2

                 A1

                 S1

                 S2

                                                            (Fig. 3)

                CLK2         

                A1

               S1

           ...