Clock Domain Crossing Signals and Gate Level Simulation (18-Nov-2008)

Abstract 

This paper presents an approach to simulate various possible silicon behaviors arising due to timing violations on synchronizer flops at clock domain crossing (CDC) boundaries during Gate Level Simulations (GLS) and catch synchronizer related design and timing issues during the design phase.

Background

Most recent integrated circuit designs include multiple clock domains. Designers implement synchronizers on clock domain crossing (CDC) signals to avoid propagation of metastablility across different clock domains. The CDC signals are not timed during STA (Static Timing Analysis) and may cause ignorable timing violations during gate level timing simulations. Special care must be taken during gate level simulations (GLS) to handle these violations.

Conventional GLS simulation approaches (SDF modification or Xfilters) don’t simulate all possible silicon behaviors at clock domain crossing (CDC) boundaries arising due to timing violation at first synchronizer flop. They just avoid X propagation and always sample correct/expected data and hence can never check any design issues because of metastability at asynchronous boundaries.

Conventional approaches don’t have the means to handle synchronizer flops that have some input signal (D/Rb/Sb, where D is Data input, Rb is async reset and Sb is async set input of D Flip-Flop) driven from synchronous domain while other from asynchronous domain. In such a scenario, conventional approaches will mask/ignore legitimate violations on synchronous domain signal too and thus can hide real design issue.

This paper presents a new approach to handle these ignorable timing violations on synchronizer flops while enabling users to simulate all possible scenarios that may occur on synchronizers on actual silicon, which was not possible with conventional GLS approaches (Xfilters and SDF-modification).

Body

Figure 1 shows a normal 2 stage synchronizer with data “d1” coming from clock domain “clk1” and being sampled by flops working on “clk2”, assuming “clk1” is faster than “clk2”. Same can be extended to various other clock relationships.

Figure 1 : Two-Flop Synchronizer

If clk1 and clk2 don’t have constant phase relationship, then change on data “d1” might violate setup/hold time of flop D1, resulting in metastable output “q1”. Multi-stage synchronizer (2 stage here) ensures that metastability doesn’t propagate through the design. But this metastability due to setup or hold violation can result in different design scenarios. In case design is sensitive to the clock edge on which data gets sampled or design is such that outputs of multiple synchronizers converge and design has assumed definite timing relationship between different converging CDC signals, then it becomes a necessity to si...