The IP.com Prior Art Database
English (United States)
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Buffer Retiming within a Synthesis Environment
Retiming is a method for improving the worst-case timing path by balancing the overall delays between latch stages within a design. This method has been a well-known optimization method for many years however it is not widely automated because of the current methodology that requires a valid, readable vhdl to pass verity and timing paths that stay consistent between each run.
Synthesis is capable of implementing retiming but automated updates to the vhdl create a macro that is incomprehensible for human eyes. Thus, there is not a current system that both offers an automated method of retiming within our current methodology.
The proposed system uses modified entities within the vhdl that are similar to current latch instantiation but with a modified parameter in the generic map statement to enable synthesis access to control the latch polarity. This allows synthesis to implement logic retiming automatically and then update the vhdl directly without having to edit any of the signal names throughout the vhdl file. The parameters can be loaded either within the vhdl itself or in an external include.
Figure 1 below shows a simple example of a timing path which occurs often that can be improved with automatic buffer retiming both an improvement in power and timing.
Figure 1 shows a common implementation for a macro PO. In some cases, three inverters are needed to drive the macro output but in many cases, only two inverters are needed. When that happens, synthesis must choose between either a one inverter solution or a three inverter solution. Thus, if one inverter is not enough to drive the macro PO, an extra inverter is put in the logic path which hurts timing.
The only current solution to thi...