Buffer Retiming within a Synthesis Environment

Proposed is a system and method for implementing synthesis retiming for the buffering solutions within our current methodology that does not render the vhdl unreadable to a human. Ultimately, this process allows for synthesis to flip the polarity of a latch within the vhdl with simple updates instead of having to trace through the logic and change net inputs. There are three instances within synthesis that do not produce optimal results. The first occurs when there is a PI feeding into a latch. In this case, design rules dictate that at least one inverter must be present before the input to the latch. But, there are cases where just one inverter causes the polarity of the data to be incorrect so a second inverter must be added which is not optimal. The second case is just like the first case except for a PO. There are many instances where only two inverters would be needed to drive the output of the latch but the polarity of the latch requires a third inverter which adds extra delay to the timing path. The third case where the proposed solution can offer timing improvements is on an internal latch with larger fan-out requiring a buffer tree. The number of buffers in the tree is often dictated by the polarity of the latch or by a specific logic cone in that path and thus, better solutions would be attainable if synthesis was able to control the polarity of the latch. The system uses predefined logic structures that have a variable passed to them controlling the polarity of the signal that is latched. Thus, when synthesis changes the implementation of the logic for retiming, the only update to the vhdl that is required is a parameter override statement beside the latch instantiation to update the vhdl to pass verity. Using this methodology, logic designers can create readable vhdl enables synthesis to implement buffer retimming.