Low Duty Cycle Distortion Receiver Design (18-Aug-2009)

Described is a solution to have a low duty cycle distortion receiver under extensively fluctuated power supplies which has a low product cost. The drawback could be running high DC currents which are controlled by a power supply independent current reference circuit.

    The receiver circuit is designed to minimize the duty cycle distortion (DCD) under extensive fluctuations of power supplies of VDD, DVDD, temperature, and process corners while maintaining short delay time and fast rise and fall edges of a rather simple circuit scheme.

    The wide operating ranges are: VDD

, DVDD

, Temperature

, Process corners

; the receiver (as shown in Figure 1) is designed to operate under those wide ranges while it is still able to execute the following functions. The receiver has three stages. The first stage is in DVDD domain; the second and third stages are in VDD domain. The input signals are Pseudo-ECL (PECL) with the waveforms of +/- 200mv referencing to VREF equivalent to .7*DVDD. The input signals can be a pair of complementary PECL signals feeding to PAD and PADN; or, one is PECL feeding to PAD and another is VREF feeding to PADN. The output, Z swings rail-to-rail in VDD domain. After the translation of first stage, the outputs are OUTP and OUTN which swing from low voltage around 0v to high voltage around 500mv. Running through its three levels of amplifiers, the second stage eventually converts it inputs swing (~500mV) to generate a rail-to-tail swing (VDD) at the output, OUTZ. With two levels of inverters, the third stage operates as a buffer for driving bigger load at the output, Z. All three stages are designed to minimize DCD with rather simple circuit schemes.

Ȉ ˇ

    The following circuit design example implements with the thick gate-oxide transistors of IBM* 45nm SOI technology. PAD is fed with input, PECL and PADN is fed with input, VREF; hence the inputs are not symmetrical (see Figure 2). For the following schematics, PMOS and

NMOS transistor symbols are shown with and without bubble,

accordingly.

1

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    In Figure 2, T0 (80u), T1 (16u), T2 (1u), T3 (1u), T6 (4u) and T7 (4u) are the current mirror scheme referenced to the REC

_iref

designed with power-supply-independent current reference circuit in order to source 200uA constant current with small impact from DVDD fluctuation. T0 is designed to generate 1mA for nominal case. T4 (8u), T5 (8u) and TP0 (32u), TP1 (32u) are the two differential pairs of circuit to bring in the inputs, PAD and PADN. R0 (430-ohm), R1 (500-ohm) are the output resistors; since the inputs are not symmetrical, R0 and R1 have to be skewed to generate the rather symmetrical outputs, OUTP and OUTN. Therefore, although the inputs and the first stage power supply are fluctuated extensively (1.6v-2.1...