A method to select and operate in a different voltage mode to produce a single constant output impedance on a single high speed transceiver logic circuit. (16-Sep-2009)

A method to select and operate in a different voltage mode to produce a single constant output impedance on a single high speed transceiver logic circuit .

Disclosed in this novelty is an integrated circuit with the ability to perform in two very different voltage domains and be able to produce the same output impedance with a terminated output load.

The output enable (OE) determines the operational state. The mode control (MC) defines the voltage state. The state of the mode control drives the predrive state which is comprised of a combination of nand and nor. There's a combination that represents each voltage state. The output of the predrive nands, drives the output stage of a set of staggered pFET.

Similarly, the output of the predrive nors, drives the output stage of a set of staggered nFET. The nets of the output stage are then buffered or compensated by a resistor to the pad to provide the proper load. This high speed transceiver logic (HSTL) design was done to satisfy the JEDEC standardization spec EIA/JESD8-6. This design was completed with the following objectives; to satisfy a class I or a class II requirement of 8mA or 16mA output impedance respectively with the ability to function in two independent voltage domains with the aide of the voltage reference (VREF).

This design satisfies Jedec Standard HSTL(1.8v)/(1.5v) Class I Driver.

This cell is a noninverting bidirectional driver/receiver that operates over a VDD range of
0.9-1.1 V and a DVDD range of 1.4-1.6v for BIC operation(MC1518=1) or 1.65-1.95 V for standard HSTL(MC1518=0). Off-chip termination requires 50-ohm (50-ohm at far end) to DVDD/2. This I/O requires the use of the following cells: VREFR1

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_AA (I/O cells that using a VREF supp...