Wear-leveling technique for EEPROM devices (16-Sep-2009)

Wear-leveling technique for EEPROM devices

Proposed is an invention that implements a novel wear levelling tecnique that prevents the formation of data "hot" spots in EEPROM devices. This increases the life of such devices.

An advantage of using EEPROM technology is that a solid-state, non-volatile memory is provided, which can be repetitively reprogrammed. Each EEPROM cell includes an electrically floating gate positioned over a substrate channel between source and drain regions. A thin gate oxide layer separates the floating gate from the substrate. The threshold level of the cell is controlled by an amount of charge that is placed on the floating gate. If the charge level is above some threshold, the cell is read to have one state, and if below that threshold, is read to have another state.

The desired floating gate charge level is programmed by applying an appropriate combination of voltages to the source, drain, substrate and a separate control gate, for a designated period of time, in order to cause electrons to move from the substrate to the floating gate through the gate oxide layer. Current leakage from the floating gate is very small over time, thereby providing permanent storage. The charge level on the floating gate can be reduced by an appropriate combination of voltages applied to the elements described above, but it is preferable to include a separate erase gate that is positioned adjacent the floating gate with a thin layer of tunnel oxide between them.

A large number of such cells form a memory. The cells are preferably arranged on a semiconductor integrated circuit chip in a two-dimensional array with a common control gate provided for a row of such cells as a word line and the cells in each column having either their drain or source connected to a common bit line. Each cell is then individually addressable by applying the appropriate voltages to the word and bit lines that intersect at the desired cell. Rather than providing for such individual addressing for the purpose of erasing the cells, however, the erase gates of a block of cells are generally connected together in order to allow all of the cells in the block to be erased at the same time, i.e., in a "flash".

In operating such a memory system, cells can be rewritten with data by either programming with electrons from the substrate or erasing through their erase gates, depending upon the state in which they are found and the state to which they are to be rewritten. However, flash EEPROM systems are generally operated by first erasing all of the cells in a erasable block to a common level, and then reprogramming them to desired new states.

Flash EEPROM mass storage systems have many advantages for a large number of applications. These advantages include their non-volatility, speed, ease of erasure and reprogramming, small physical size an...