A Method for Grinding Silicon with 3M™ Trizact™ Diamond Tile (16-Sep-2009)
The advantages of using 3M™ Trizact™ Diamond Tile abrasive pads for silicon grinding is high removal rates on existing CMP tools. One potential advantage is TDT could be incorporated into a multistep process that includes a high rate (TDT) step followed by a lower rate (CMP) polish step, carried out sequentially on a single tool (e.g. Mirra), optionally using a slurry with TDT in one or both steps. The high rate step would provide bulk removal of silicon and the CMP step would reduce the finish on the silicon to acceptable levels. Down pressure and platen speed have a strong effect on rate. Higher workpiece pressure or platen speed resulted in higher silicon removal rate. No trends were observed in surface finish as measured by the Tencor profilometer due to the DOE process conditions.
A Method for Grinding Patterned Silicon Wafers with a Fixed Abrasive
Bruce Sventek basventek@mmm.com Technical Application Specialist 3M Company, St. Paul MN.
John Gagliardi JJgagliardi@mmm.com Lead Technical Specialist 3M Company, St. Paul MN.
This Paper describes a method for grinding and thinning silicon wafers using 3M™ Trizact™ Diamond Tile (TDT) abrasive pads, a type of fixed abrasive. This method is particularly useful for wafer packaging applications.
Background Summary
The performance of integrated circuits has seen a steady, exponential increase in the computer industry for the past 40 years. The first 15 years following the invention of the integrated circuit in 1959 was a period of even faster growth after which the industry settled into a pace of a new generation of circuits every three years. Each successive generation of circuits has had more than twice the speed, four times the number of transistors and four times the memory of the previous one. This growth pace has been the source for faster and more powerful growth every year. Today's common computers now pack more power than yesterday's supercomputers, and at a small fraction of the cost. It is believed, however, that transistors based on the existing technology, termed CMOS (for complementary metal-oxide semiconductor), may soon reach a limit in how much they can shrink. At some point, this steady progress will have to slow and finally stop, or continue only with a fundamentally different technology.1
One of the approaches that many semiconductors companies are looking at to continue to maximize the amount of circuitry in a unit area of chip space is through Wafer Stacking or Packaging. In this approach, chips are stacked on top of each other in order to provide a higher circuit density. Additional processing of semiconductor wafers needs to take place for Wafer Packaging to be accomplished. Through silicon via (TSV) are generally required so that the various stacked chips can communicate with one other. In order to make TSVs the silicon needs to be thinned. 1
A critical step in the process to make TSVs is the silicon grinding step. Companies
use a grinding machine that typically uses a grinding cup wheel, available from Disco, Koyo, and others. Although the performance is good on bare silicon, the cost of consumables and equipment costs are high. Additionally, these high cost wheels can load and be damaged by metals used for TSVs.
1. Eric Lerner / http://domino.watson.ibm.com/comm/wwwr_thinkresearch.nsf/pages/cmos398.html
There are a number of reasons for wafer thinning including but not limited to:
Die stacking / Through silicon via (TSV) wafers
Dice before grind (DBG)
Superior electrical and thermal properties (Heat dissipation) RFID (Smart cards)
3M™ Trizact™ Diamond Tile (TDT) abrasive pads run on a CMP polishing tool, rather than a typical grinding tool, is an option for these applications. Data d...
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