Optimal Layout Parasitic Rxtraction Deck GenerationTtechnique for aTtechnology With Multiple BEOL's and a Common FEOL and/or Partially Common BEOL. (17-Sep-2009)

Optimal Layout Parasitic Rxtraction Deck GenerationTtechnique for aTtechnology With Multiple BEOL's and a Common FEOL and/or Partially Common BEOL.

1

Method and System for Generating One or More Technology Files for Parasitic Extraction Tools

Abstract

A method and system for generating one or more Technology Files (TFs) for parasitic extraction tools is disclosed. The method includes saving common information of TFs created earlier for inclusion in other TFs.

Description

Disclosed is a method and system for generating one or more TFs for parasitic extraction tools. Parasitic extraction tools may be for example, but not limited to, Front End Of Line (FEOL) or Back End Of Line (BEOL) integrated circuit design tools. Usually, one or more TFs for parasitic extraction tools are generated from the lowest substrate level to each of one or more stacks in an integrated circuit design. Thus, each stack requires a separate TF to be created as illustrated in Fig. 1.

Figure 1

1

However, in many cases, there are one or more common layers between the one or more stacks. An instance of common layers between the one or more stacks is illustrated in Fig. 2. As the one or more common layers for each stack is calculated separately, it results in repetitive counting of the one or more common layers.

Figure 2

Also, usually, each TF is generated as independent run i.e. one at a time. Thus, this leads to waste of time when considering the number of stacks offered by a particular technology and the various process points that are created. For example, a single vendor TF generation can take up to 3 - 6 hrs distributed across ten 64 bit CPUs. By way of another example, a single ERIETF can take up to 3 hrs on a single CPU.

2

Disclosed is a method and system for saving common information of the one or more TFs created earlier for inclusion in other TFs. Fig. 3 illustrates a method of creating TFs for the one or more stacks.

Figure 3

According to Fig. 3 there is information associated with each of Stack 1, Stack 2 and Stack 3. Information may include for example, but is not limited to, one or more of conductor thickness, dielectric thickness, width and space. A part of the information associated with Stack 1, Stack 2 and Stack 3 is common to each of Stack 1, Stack 2 and Stack 3. Another part of the information associated with Stack 1, Stack 2 and Stack 3 is specific to Stack 1, Stack 2 and Stack 3 respectively. The method includes step of coll...