Microprocessor Predictive Power Supply Droop Compensation (17-Sep-2009)
As microprocessors become more complex and consume more power, the problem of keeping a constant voltage across the entire chip is increasingly difficult. A technique for predicting power intensive operations and mitigating the influence of these operations is described.
Microprocessor Predictive Power Supply Droop Compensation
On chip voltage variation presents challenges to IC designers. Voltage droop makes timing closure more challenging, and using worst case assumptions ultimately results in higher power consumption than necessary. For microprocessors power supply droops are usually dependent upon the state of the processor and instructions being executed. Worst case voltage droops can be reduced by predicting which instruction/state combinations will have the greatest effect and taking action to compensate.
Methods to compensate for voltage droop include: local clock frequency change, local voltage control, or the addition of local no-op instructions. Voltage droop prediction is accomplished through the use of one or more power look up table circuits is placed in chip. The power look up table stores instructions/processor states for known voltage droops. When a known instruction/processor state matches the stored entry in the look-up table, a flag or interrupt is issued to enable droop mitigating action. Techniques to populate power lookup table include: writing patterns to detect voltage droops in the lab, hard coding entries into power lookup table power lookup table, searching power lookup table entries before it is presented to processor for execution. The power lookup table (CAM/RAM) can also be updated directly in the field.
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