Preparing your result...
Loading...
Press Esc to dismiss this message

Visual Monitor for Charging Damage (Lateral Potential Difference) (17-Sep-2009)

Thumbnail
IP.com Prior Art Database Disclosure (Source: IPCOM)
Disclosure Number IPCOM000187749D dated 17-Sep-2009
Originally published in Prior Art Database
Disclosed by: IBM
Country: Undisclosed
Disclosure File: 3 pages / 99.0 KB / English (United States)

This article teaches using a structure and method to detect inline charging damage by ?optical? inspection of a small gap (over which arcing may have taken place) and/or a narrow line (which may have fused open) during an inline charging event on an SOI wafer

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 61% of the total text.

Page 1 of 3

Visual Monitor for Charging Damage (Lateral Potential Difference)

The structure is composed of

An antenna (a relatively large conductor whose size is designed related to product design groundrules) placed in very close proximity (at or near photolithographic minimum) to a second, identical antenna
An antenna (a relatively large conductor whose size is designed related to product design groundrules) connected with a small link (at or near photolithographic minimum) to a second, identical antenna

The method is to


Include the appropriate set of the above structures in a non-critical location on the reticle
To include each level of interest
To examine the link and gap regions for physical damage with PLY, or inline wafer inspection

There are a variety of methods of detecting charging damage.

Examining the actual product given an
electrical fail signature is expensive and time-consuming, and may give little to no information about the sector which caused the problem. Observing arcing damage on actual product is rapid and instructive, but
there is no control of the structure, and no consistency from one design to another.

Electrical test of scribe line structures can be effective, but is usually limited to testing at the end of the process
and if separation by sector is desired, requires a lot of space for multiple antennas

Non-product test wafers have a number of drawbacks, such as cost, limited resusability, and only indirect correl...

(Source: IPCOM)
First page image
(Source: IPCOM)