At Speed Automated Scan Chain Diagnostics Process for Manufacturing Wafer Test (01-Oct-2009)
Structural testing of scan based designs of VLSI devices is highly dependent on the functionality of the scan chains and the associated latches. These scan chains are used to stimulate and observe the state of the combinational logic within device and used during the diagnostic process to localize to the failing defect when the device fails. Current scan chain diagnostic solutions depend on logging large volumes of test result data and extensive off-line diagnostic processing. These existing diagnostic methods are often inaccurate and require relatively long time from test to diagnostic resolution. This paper proposes a unique dynamic at-the-tester scan chain diagnostic method intended for use in a automated manufacturing test flow. This diagnostic technique utilizes custom scan diagnostic patterns to instantaneously identify the first failing latch of a stuck-at scan chain. The concept also lends itself to high accuracy diagnostic resolution and is compatible with an adaptive test flow process.
At Speed Automated Scan Chain Diagnostics Process for Manufacturing Wafer Test
The main concept of this invention disclosure is to interactively diagnose scan chain fails at the tester using a subset of predefined patterns. It accomplishes this by combining several scan pattern generation and diagnostic techniques including the "Dynamic Scramble Pattern Generation Method" [Ref. 4], the "Look Ahead Scan Diagnostic Method" [Ref.3]and the "Scramble Based Look Ahead Diagnostic Scan Pattern Generation" [Ref. 7] to solve the problem of diagnosing broken or stuck-at scan chains and rapidly localizing the defects to a failing Shift Register Latch (SRL) during in-line and manufacturing test . These custom scan diagnostic patterns can be generated prior to test and invoked as required during test or can be dynamically generated at the tester using some of the techniques described in the references. An extracted subset of these patterns is then applied to the device under test for the "common" mode failing scan chains to localize the cause of failure using some of the outlined diagnostic techniques.
These patterns could typically include two pairs of patterns for each latch in the scan chain being stimulated during the diagnostic process. The first pair of patterns would be needed to stimulate a latch in a scan chain whose scan-out is stuck-at a "0" state, while the second pair would be needed to diagnose a scan chain stuck-at a "1" state. Both pairs of patterns would provide the capability to broadside or laterally stimulate each latch to the "0" and "1" state. These pairs of patterns can further be generated for each latch of interest in one or more scan chains and verified off-line using good machine simulation (GMS) or on the tester using boot-strapping techniques with a "good" reference device. A process similar to the look ahead method can be used to prepare and verify some or all the necessary diagnostic patterns ahead of time and conditionally invoked them during manufacturing test as required. The major benefits of this automated diagnostic approach is that it provides instantaneous diagnostic resolution to the failing latch with a high degree of accuracy and does not require logging of large volumes of test results data.
Advantages & Benefits:
At-the-tester high resolution scan chain diagnostic calls.
1.
Complements adaptive test methodology. Test flow adapted by on-the-fly
2.
diagnostic results.
Utilizes unique pattern generation for each individual latch enabling binary
3.
search for specific failing latch.
Invokes dynamic selection of patterns during execution for specific scan
4.
fail.
Can be invoked with predefined "common" mode scan chain fail criteria
5.
(e.g. if a specific scan chain fails on more than N chips on a wafer)
Identifies first failing latch per chain.
6.
For individual look-ahead stored patter...
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