A Device/Package Configuration Based Leakage Power Reduction Technique with improved PMC Protocol (04-Nov-2009)
To reduce design and packaging costs, increasingly SoCs are developed to satisfy different demands of multiple customers. As a result, some customers do not need the complete functionality provided by the existing solution but need only a part of it. This in-turn leads to inclusion of logic which might be needed by one customer and not by others. Although, this extra logic is not used in lower variants of the SoC, it contributes to the overall leakage as it shares the same power network as the rest of the logic. A solution is being suggested to reduce the leakage in lower variants by using the package configuration information.
A Device/Package Configuration Based Leakage Power Reduction Technique with improved PMC Protocol
Abstract: To reduce design and packaging costs, increasingly SoCs are developed to satisfy different demands of multiple customers. As a result, some customers do not need the complete functionality provided by the existing solution but need only a part of it. This in-turn leads to inclusion of logic which might be needed by one customer and not by others. Although, this extra logic is not used in lower variants of the SoC, it contributes to the overall leakage as it shares the same power network as the rest of the logic. A solution is being suggested to reduce the leakage in lower variants by using the package configuration information.
1. Introduction
As per
Moore
’s law, we have seen the feature size being scaled down but the average chip size has increased over the period of time as indicated in the Fig 1 below:This increase in chip size is the result of incorporating more and more functionality into a single SoC. This leads to increased complexity, production cycle time and thus the associated development cost. The cost involved in the development, packaging and activities related to ‘Ramp To Production’ constitute a major portion of the total cost.
While designing to fulfill a number of customers’ requirements, their requirement profile can be classified as “largely overlapping with slight specific requirements.” One solution that caters to the above mentioned scenario is a SoC which meets the superset of customers’ requirement and then to market the solution to all the interested customers and judiciously provide the functionality that just fits into their requirement. Now, to inhibit the customer from using all the functionality, the die is packaged in different packages with the controlled access to spectrum of available applications. This is done through packaging the device into multiple packages. Fig. 2 shows an example of the same, where a single die is shown to be packaged into three package variants. While the higher pin package provides all (or most of) the functionality, the smaller pin packages provide just right functionality. Thus, we can control the available memory, supported communication protocols, peripherals, ADC/DAC channels etc to a customer who does not seek them.
Fig2: An e.g. of a die going into different Package variants
2. Motivation for saving Leakage Power
This technique enables us to develop a single SoC and sell multiple variants to various customers. It also reduces the cycle time but calls for the integration of more logic/ IPs than required for a limited variant. Now the customer might be able to use the solution in ...
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