Contamination Gettering Technique For Silicon-On-Insulator (SOI) Wafers (16-Nov-2009)

CONTAMINATION GETTERING TECHNIQUE FOR SILICON-ON-INSULATOR (SOI) WAFERS

TECHNICAL DISCLOSURE

     
Contamination in silicon substrates reduces gate oxide quality, resulting in reduced reliability. With Silicon-On-Insulator (SOI) wafers contamination is accumulated in the top Silicon (Si) layer due to blocking by a Silicon Oxide (SiO2) layer buried in the substrate. Contamination in the top Si layer is accumulated in non-harmful locations. These locations can be Shallow Trench Isolation (STI) regions. Implanting non-diffusing atoms (e.g., Germanium (Ge)) under STI regions during wafer processing creates damage which collects contamination from the top Si layer. Spacers are added to avoid junction leakage current at side walls of STI regions due to implants.

     FIG. 1 below is a cross-sectional view of an example SOI wafer 100. SOI wafer 100 includes buried SiO2 layer 102, STI regions 104 and spacers 106. Non-diffusing atoms are implanted in sidewalls 108 of STI regions 104 to create damage that collects contamination from the top Si layer of SOI wafer 100. Spacers 106 are used to prevent junction leakage current due to implants in side walls 108 of STI regions 104.

100

¹⁰⁶104108

Buried SiO 102

FIG. 1