Method and System for Automatic Diagnosis of Parasitic Extraction (PEX) Deck Development. (16-Nov-2009)

Method and System for Automatic Diagnosis of Parasitic Extraction (PEX) Deck

Development.

Disclosed is a method and system for automatic diagnosis of errors during Parasitic

Extraction (PEX) rule/deck development.

Determining electrical parasitic elements such as line capacitance, resistance and inductance in an Integrated Circuit (IC) design is a crucial process for the success of IC designs. This process is called layout Parasitic Extraction (PEX).

Generally, PEX deck verification is performed by running multiple tests using multiple test cases (as shown in Fig. 1). Errors found during the PEX deck verification are communicated to a developer after running the multiple tests. The developer must wait until all individual tests are completed to discover errors. Also, since a common "stop" path is used for all of the multiple tests, for any errors found, all the multiple tests need to be restarted. This process is time consuming, error prone and difficult to debug.

Figure 1

Fig. 2 illustrates a method and system for PEX deck generation and verification. Information regarding Design Manual, process assumption and device list is collected. The information collected is parsed and verified. Thereafter, the verified information is provided to a PEX deck generator in the form of standardized information. The PEX

1

deck thus generated is automatically verified to detect any errors.

Figure 2

Fig. 3 illustrates an instance of the method and system for automatically verifying a PEX deck by running a Double-Counting Test. Errors gene...