Gated Direct Read of Dynamic Random Access Memory Cells Using High Transfer Ratio (16-Nov-2009)

Gated Direct Read of Dynamic Random Access Memory Cells Using High Transfer Ratio

Disclosed is a method and apparatus for gating direct read of Dynamic Random Access Memory (DRAM) cells by using high transfer ratio. The method and apparatus utilize Silicon on Insulator (SOI) embedded DRAM macro with micro Sense Amp (µSA) architecture for gating direct read of the DRAM cells.

A circuit diagram depicting the disclosed apparatus is shown in Fig. 1.

Figure 1

The disclosed method and apparatus involves utilizing µSA architecture (6T µSA) for DRAM cells. The µSA architecture relies on a high transfer ratio during a read to create a large voltage swing on a Local Bit-Line (LBL), which is large enough to be sampled with the single ended µSA. One or more µSA architectures are connected to multiple DRAM cells on a single, relaxed pitch line. For example, thirty three DRAM cells may be connected to µSA architecture on a single, relaxed-pitch M1. The µSA transfers data to or from a Global Sense Amp (GSA) via two Global Read/Write Bit Lines (RBL/ WBL). Each GSA, in turn, may service eight µSAs and transfers data to or from a Data Sense Amp (DSA) via local M1 data lines.

To achieve a high transfer ratio, a 18fF Deep Trench (DT) cell is used in combination with a 4fF LBL. The low capacitance LBL is achieved using a short (33 bits) bitline and a compact sense amp layout comprised of logic-type devices. The single-ended LBL enables relaxed M1 pitch, increasing line to line space by three times. The µSA architecture is enhanced with three additional FETs. Further, the µSA is configured with negative channel FET (nFET) stack for reading, a positive channel FET (pFET) stack for

1

writing and refreshing a '1', a write '0' nFET (W0), and finally a pre-charge nFET (PC) for holding unselected LBLs at ground.

The pFET header (PH) is added to reduce standby power by stacking and AC power is reduced by preventing unnecessary transitions on unselected LBLs. The nFET pre-charge device prevents partially selected LBLs from coupling below ground, causing retention time degradation and saves power by avoiding WBL transitions previously required for LBL pre-charge. Overall, LBL power is reduced by a factor of 8 and WBL power is reduced by an average of 33%. The nFET footer (NF) is added to increase read '1' margin by gating off the unselected read heads, reducing leakage by a factor of 8, which enables use of a lower threshold voltage (V_T ) read device having increased overdrive and reduced V_T variation. The nFET footer (NF) and nFET pre-charge (PC) additionally provide independent timing control of pre-charge and Read Enable, allowing Read Enable to be delayed and signal development to occur without exposing RBL to unnecessary leakage that could reduce the signal ma...