Configurable Rank Translation (18-Jan-2010)
This pertains to the design of DRAM memory controllers. In a computer system, memory may consist of multiple and separate DRAM modules (DIMMs for instance) known as ranks. To access a rank a memory controller will assert an individual chip select line. A memory controller may control one or more ranks of memory. In certain computer architectures it is advantageous to be able to populate different ranks whilst leaving others unconnected. It can be desirable for the arrangement of which ranks are connected or unconnected to be flexible. However typical memory controller designs may not permit this. They may specify that only certain rank combinations are permissible. This article describes a memory controller design which allows any configuration of ranks to be used.
Configurable Rank Translation
This pertains to the design of DRAM memory controllers. In a computer system, memory may consist of multiple and separate DRAM modules (DIMMs for instance) known as ranks. To access a rank a memory controller will assert an individual chip select line. A memory controller may control one or more ranks of memory.
When memory is to be accessed via the controller, an address is presented. The address is typically sub-divided into portions. Certain bits of the address may specify the bank address of DRAM to be accessed and other bits may specify the column address and row address. Lower order address bits are typically used for these. As ranks are typically the largest subdivision of memory (in terms of size), the higher order address bits specify the rank to be accessed. Figure 1 illustrates how the logical address presented to the memory can be broken down into, amongst other things, bank, column, row and rank addresses (collectively, the physical address).
Logical Address
Higher order address bits
Rank Address
Row Address
Column Address
Bank Address
Cacheline Offset
LSB
Figure 1 - Typical breakdown of a logical address into physical DRAM address components
For a conventional memory controller, in order to present a contiguous address space beginning at logical address 0 up to a given number of ranks, n say, then all ranks from rank 0 to rank n-1 must be populated with memory modules. For example, a computer system may require 4 ranks of memory to be under a single memory controller as in Figure 2a.
Processor
Processor
Memory Controller
Memory Controller
R a n k 0
R a n k 1
R a n k 2
R a n k 3
R a n k 0
R a n k 1
... whilst ranks 2 & 3 must be left unused
Memory modules populated on all 4 ranks
Memory modules
can only be populated on ranks 0 & 1 for a two-rank configuration...
(a)
(b)
Figure 2 - 4 Rank and 2 Rank memory configuration
If another computer system required only 2 ranks of memory and used the same memory controller, then in order to maintain a contiguous address space
beginning at logical address 0 up, ranks 0 and 1 would have to be used (leaving ranks 2 and 3 unconnected) as in Figure 2b. It would not be possible for, say, ranks 0 and 3 to be used (leaving ranks 1 and 2 unconnected) because the logical address space would no longer be contiguous. A logical address selecting either rank 1 or rank 2 would not map to any physical memory. There would therefore be a gap between the last logical address in the range of rank 0 and the first logical address in the range of rank 3. A memory access crossing a rank boundary would be forced to be split up into two accesses which is not desirable for performance.
In certain computer architectures it is advantageous to be able to populate different ranks whilst leaving others unconnected. It can be desirable for the arrangement of which ranks are connected or unconnected to be flexible. For example, whe...
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