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System and Method for Verifying the Context Switch of a Multiprocessor System (02-Feb-2010)

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IP.com Prior Art Database Disclosure (Source: IPCOM)
Disclosure Number IPCOM000192765D dated 02-Feb-2010
Originally published in Prior Art Database
Disclosed by: IBM
Country: Undisclosed
Disclosure File: 3 pages / 231.0 KB / English (United States)

A system and method for verification of the context-switching feature of a multi-processor environment is disclosed herewith. Context switching is the primary mechanism leveraged by the Operating System to schedule various processes. In a multiprocessor environment, the switching of contexts assumes greater significance. In Real-time systems, rapid context switching is of utmost importance. The methodology proposed here recreates the Operating system scenario enabling verification of the context-switch mechanism.

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System and Method for Verifying the Context Switch of a Multiprocessor System

The context switching mechanism outlined here uses a number of testcases. This recreates the Operating System scenario wherein various processes share CPU time running on time slicing and various other scheduling algorithms.

The Decrementer register is loaded with a range of values from very tiny to reasonably large values to ensure that rapid and sluggish context switching are both verified thoroughly. The tiny Decrementer values exercise the context switching mechanism vigorously.

The testcases are scheduled on various processors by a lightweight dispatcher that also computes and loads Decrementer value based on user specification.

Modules of the Test Program:

CPU Queues: Every CPU is designated with a queue. This queue holds the testcases scheduled to execute next and the details of the context saved for these testcases.

Lightweight Dispatcher: The Lightweight Dispatcher handles the task of scheduling testcases to various CPU queues. It is also the responsibility of this scheduler to calculate and load appropriate Decrementer values to each CPU.

Decrementer Interrupt Handler: The Decrementer interrupt triggers the context switching on the CPUs. The interrupt handler routine saves the context of the current testcase. The Interrupt handler then passes on the task of scheduling the testcase and its saved context on another CPU to the Lightweight Dispatcher. Then the context of the testcase in the corresponding processor queue is loaded and execution of the next testcase begins on...

(Source: IPCOM)
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(Source: IPCOM)