A Method and System for Asynchronously Executing a Federated Search Query Across One or More Repositories (02-Feb-2010)

A Method and System for Asynchronously Executing a Federated Search Query Across

One or More Repositories

Disclosed is a modified Phase Lock Loop (PLL) with an improved stability.

Fig.1 illustrates a block diagram of the modified PLL as proposed herein. The modified

PLL includes a frequency clamping circuit. The frequency clamping circuit limits output

frequency of Voltage Controlled Oscillator/ Current Controlled Oscillator (VCO/ICO) by

limiting voltage/current supplied to the VCO/ICO.

Figure 1

The frequency clamping circuit may be one of a voltage comparator based and a

current steering based clamping circuit.

Fig. 2 illustrates the voltage comparator based frequency clamp circuit.

Figure 2

The frequency clamp circuit for VCO is shown in Fig. 3(a). An input voltage, V_in is

supplied to the frequency clamp circuit from the charge pump (as shown in Fig. 2) and V

out is an output voltage supplied to the VCO. A threshold voltage V_th is defined as a

control voltage for clamping the frequency of the VCO. In normal operation, V_in is lower than V_th, therefore, output of voltage comparator U1 is at logic low which turns OFF the

1

N-Type Field Effect Transistor (NFET) N2. Further, the output of inverter U2 is at logic

high which turns ON NFET N1 so that V_out is equal to V_in. Now, in a startup procedure, an overshoot may occur, in which case, V_in may be higher than V_th. Due to this, the output of the voltage comparator U1 is at logic low which turns OFF N1. Also, the

output of U2 is at logic high which turns on N2 due to which V_out becomes equal to Vth.

Therefore, in a way V_out is always restricted to Vth. In this way, the VCO output frequency never exceeds the limit set by V_th.

Similarly, a clamp circuit for ICO is shown in Fig.3(b). I_in is input current from the charge pump and I_out is output current to the ICO. Further, a threshold current I_th is defined for clamping the frequency of ICO.

P1, P2 are the current mirror with unity current gain, therefore, current through R1 is I_in

and the voltage on R1, VR is I_in*R. P1 and P3 can be formed as a pair of the current mirror depending on the ON/OFF status of PFET p...