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Method and System for Reducing the Potential Barrier Between a Photodiode and Transfer Gate in CMOS Image Sensor (02-Feb-2010)

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IP.com Prior Art Database Disclosure (Source: IPCOM)
Disclosure Number IPCOM000192789D dated 02-Feb-2010
Originally published in Prior Art Database
Disclosed by: IBM
Country: Undisclosed
Disclosure File: 4 pages / 81.5 KB / English (United States)

A method and system for reducing the potential barrier between a photodiode and a transfer gate in a Complementary metal–oxide–semiconductor (CMOS) image sensor for improved image lag and fast charge transfer efficiency is disclosed.

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Method and System for Reducing the Potential Barrier Between a Photodiode and Transfer Gate in CMOS Image Sensor

Disclosed is a method and system for reducing the potential barrier between a photodiode (PD) and a transfer gate (TG) in a Complementary metal-oxide- semiconductor (CMOS) image sensor. The method and system includes cutting a silicon recess under the poly-gate of the CMOS as illustrated in Fig. 1a. SiGe is then selectively grown in the silicon recess. Fig. 1b illustrates the stage of selective growth of SiGe in the silicon recess. Subsequently, a PD is formed into the SiGe region as shown in Fig. 1c. The presence of Ge ions reduces the potential barrier between the PD and the TG.

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Figure 1

In another instance of the method disclosed herein, graded SiGe is selectively grown in the silicon recess. The steps of this instance are as illustrated in Fig. 2.

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Figure 2

The addition of Ge to silicon reduces the band-gap between the valence band and the conduction band. Further, electron transfer rate from base into the collector is increased due to the addition of Ge to silicon. Fig. 3 illustrates a reduction in the potential barrier between the PD and the TG as compared to a higher potential barrier as shown in Fig 4. Further, with the addition of Ge to silico...

(Source: IPCOM)
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(Source: IPCOM)