Age Sensing Circuit and Method for Determining Chip Wearout (02-Feb-2010)

Age Sensing Circuit and Method for Determining Chip Wearout

Disclosed is an age sensing circuit and a method for determining chip wearout.

Typically, chip wearout is not uniform, and differentially affects circuits which have higher activity or which dwell in known problematic states. To overcome ill effects due to the wearout, a designer must pad all paths with excess margin to cover the small probability that an unknown path may slow down. This is an expensive solution which, while insuring the part remains functional, impacts overall chip performance.

Fig. 1 illustrates a schematic circuit of a standard L1/L2 Level Sensitive Scan Design (LSSD) scannable and flushable latch. The circuit includes a data-in section, a scan in section, an L1 latch, an L1 output buffer, an isolation stage, an L2 latch, and an L2 output buffer. As illustrated in Fig. 1, the performance path of the schematic circuit is DIN L1 ISO L2 DOUT. Since the SCAN PATH portion of the circuit is not in the performance path, any intentional aging of the SCAN PATH portion section does not impact chip performance.

Figure 1

1

The circuit and the method disclosed herein involve attaching a transition detector to DIN. Subsequently, the output of the transition detector is fed as a Multiplexer (mux) control for a "wear zone" that is inserted into the SCAN PATH of the scannable and flushable latch. The flush delay of each path is then compared with unstressed flush delays to evaluate age of the corresponding path.

Fig. 2 illustrates a schematic circuit of a transition detector. The transition detector is connected to th...