The IP.com Prior Art Database
English (United States)
9 pages / 421.7 KB
Framework for On Chip Application Stress
With the enablement of the sub micron technologies and the advent of Multicore devices the complexity of the SOC's is increasing manifolds, this design challenge is pushing the post silicon validation to a new extreme. Challenge is how do we rapidly validate all the application scenarios and deliver a zero defect silicon to the customer under squeezed timelines.
This paper proposes an innovative On Chip validation framework for SOC application data path validation
with high observability and control using an On Chip script interpretation framework referred to as FRAMEWORK for ON CHIP APPLICATION STRESS (FOCAS).
In this paper, we present the typical problems of debug and control using existing validation techniques and show how FOCAS solves these problems using a novel approach.
Finally, we demonstrate the effectiveness of the proposed framework by illustrating examples and comparative data from other existing application validation technique.
Sub micron design challenges are pushing the traditional validation techniques to abstract the complexity of the silicon. But with increased abstraction observability and controllability is limited whereas application data paths are particularly difficult to create without sufficient level of abstractions. The other option is to work with standard application stacks like Linux but it has its own challenges.
Glancing through the traditional validation techniques as listed below we
find them lacking in terms of one parameter or another.
So we build a set of attributes that will be used to evaluate these techniques. These will be used to select and choose the desired validation technique for Application validation.
So let us start by looking at the traditional validation techniques and evaluate each of these on desired validation attributes.
JTAG Based Testing ( D )
validation techniques is using IEEE 1149.1 based JTAG interface. JTAG is a serial interface which is available on almost all modern SOC's and which can be used to connect a Low Level Debugger (LLD) and a command converter server (CCS). CCS is a piece of software that converts high level user tests generally written in TCL to low level JTAG commands. These JTAG commands are then used to read/write or program any register or memory connected to the SOC.
1. Ease of use since tests coded in a scripting language.
2. Directed testing scenario's easily created.
TCL CCS LLD
1. Limited testing on a slow serial interface.
E.g. cannot respond to real time events like interrupts.
2. Unable to create application scenarios
Random Testing ( R )
System Control (PERL script)
Random Test Methodolog...