CPK Based IO Timing Closure in STA to Reduce Yield Loss and Test time

ABSTRACT

In any SoC design, IO timing (setup and hold timing) is met in STA (Static Timing Analysis) based on the hardware specification of the particular interface, with some pessimism.  Many times it has been found or observed that even though IO timing is met in best and worst case corners, IO timing fails or is marginal when tested in Si across PVT.  Also, the margin from IO timing check on ATE may not be sufficient for the production pattern to remove from the production flow, hence increase test time of SoC. Therefore, to aid this cause, “CPK based IO timing closure in STA” has been proposed, whereby IO timing is closed in the design phase, keeping required CPK in mind.     

BODY

·         Proposed idea:

CPK can be calculated using the below standard formula

CPK = Min [(UCL - X)/3*sigma,   (X-LCL)/3*sigma], -------------------- (1)

Where,

UCL     =  Upper cut-off limit

LCL      =  Lower cut-off limit

X          =  Mean on measured Value

Sigma   =  Standard Deviation of Measured Value of a particular spec for a particular PVT

CPK     = Co-efficient of Process Capability

Now for AC spec of any interface, UCL or LCL is known from the HW specification document.

And “sigma” of AC spec for that particular interface in typical corner can be found, by testing multiple Si on ATE for a particular technology node.   Now for targeted CPK=2, data can be put, in the above equation (1), to...