Common Design for System Specific FPGA Access

IP.com Prior Art Database Disclosure
IP.com Disclosure Number: IPCOM000218291D
Publication Date: 31-May-2012
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The IP.com Prior Art Database

Abstract

Disclosed is a method to allow common code to work with different Field Programmable Gate Array (FPGA) implementations. This approach avoids design compromises and does not force FPGAs to implement register spaces that might not be relevant to its system-specific needs. The idea is to divide FPGA register spaces into small fixed functional blocks and provide a common definition for each block.

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English (United States)

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2 pages / 31.0 KB

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Common Design for System Specific FPGA Access

In a typical design of system management firmware like Integrated Management Module (IMM), in order to communicate with different types of devices on the system board to gather system information and status, device specific code must be written to properly process the system information and respond to the current system status. Fortunately, most of the devices that IMM needs to talk to are common devices that are being used across all systems, which allows IMM to reuse and share most of its device specific codes.

This is not the case, however, for Field Programmable Gate Array (FPGA) devices because FPGAs are programmed for specific systems and they do not necessarily provide the same functionality. Some FPGA implementations handle power sequencing, fatal error reporting, and thermal info gathering, while other implementations provide access to Serial Presence Data (SPD) and inventory information. IMM accesses FPGA registers for system specific information and other system devices' status to which IMM does not have direct access. In the past designs, IMM had to provide system specific code for every system in order to correctly access and process the information obtained from FPGA. That design model created redundancy and maintenance issues, as fixes to code problems found in one system do not automatically propagate to other systems. It is more difficult to maintain multiple versions of platform specific code without deviations from the common system behavior.

The proposed design is to create a basic building block and structure to allow common code to work with different FPGA implementations. This approach avoids design compromises and does not force FPGAs to implement register spaces that might not be relevant to its system-specific needs.

The idea is to divide FPGA register spaces into small fixed functional blocks and provide a common definition for each bloc...

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