| No | Document | Title | Date |
|---|---|---|---|
| 1 |
US 7676710 B2
patent document
|
Error detection, documentation, and correction in a flash memory device | 09-Mar-2010 |
| 2 |
US 7676648 B2
patent document
|
Method for manipulating data in a group of processing elements to perform a reflection of the data | 09-Mar-2010 |
| 3 |
US 7676627 B2
patent document
|
Single segment data object management | 09-Mar-2010 |
| 4 |
US 7675778 B2
patent document
|
Memory devices having reduced word line current and method of operating and manufacturing the same | 09-Mar-2010 |
| 5 |
US 7675772 B2
patent document
|
Multilevel memory cell operation | 09-Mar-2010 |
| 6 |
US 7675526 B2
patent document
|
System and method for multi-sampling primitives to reduce aliasing | 09-Mar-2010 |
| 7 |
US 7675324 B2
patent document
|
Pre-driver logic | 09-Mar-2010 |
| 8 |
US 7675169 B2
patent document
|
Apparatus and method for packaging circuits | 09-Mar-2010 |
| 9 |
US 7675131 B2
patent document
|
Flip-chip image sensor packages and methods of fabricating the same | 09-Mar-2010 |
| 10 |
US 7675093 B2
patent document
|
Antiblooming imaging apparatus, system, and methods | 09-Mar-2010 |
| 11 |
US 7674698 B2
patent document
|
Metal-substituted transistor gates | 09-Mar-2010 |
| 12 |
US 7674683 B2
patent document
|
Bulk-isolated PN diode and method of forming a bulk-isolated PN diode | 09-Mar-2010 |
| 13 |
US 7674670 B2
patent document
|
Methods of forming threshold voltage implant regions | 09-Mar-2010 |
| 14 |
US 7674669 B2
patent document
|
FIN field effect transistor | 09-Mar-2010 |
| 15 |
US 7674655 B2
patent document
|
Semiconductor assemblies and methods of manufacturing such assemblies including forming trenches in a first side of the molding material | 09-Mar-2010 |
| 16 |
US 7674652 B2
patent document
|
Methods of forming an integrated circuit package | 09-Mar-2010 |
| 17 |
US 7673094 B2
patent document
|
Memory devices with buffered command address bus | 02-Mar-2010 |
| 18 |
US 7672171 B2
patent document
|
Non-planar flash memory array with shielded floating gates on silicon mesas | 02-Mar-2010 |
| 19 |
US 7671914 B2
patent document
|
Increasing readout speed in CMOS APS sensors through block readout | 02-Mar-2010 |
| 20 |
US 7671648 B2
patent document
|
System and method for an accuracy-enhanced DLL during a measure initialization mode | 02-Mar-2010 |
| 21 |
US 7671647 B2
patent document
|
Apparatus and method for trimming static delay of a synchronizing circuit | 02-Mar-2010 |
| 22 |
US 7671644 B2
patent document
|
Process insensitive delay line | 02-Mar-2010 |
| 23 |
US 7671459 B2
patent document
|
Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices | 02-Mar-2010 |
| 24 |
US 7671407 B2
patent document
|
Embedded trap direct tunnel non-volatile memory | 02-Mar-2010 |
| 25 |
US 7670958 B2
patent document
|
Etching methods | 02-Mar-2010 |
| 26 |
US 7670907 B2
patent document
|
Isolation regions for semiconductor devices and their formation | 02-Mar-2010 |
| 27 |
US 7670905 B2
patent document
|
Semiconductor processing methods, and methods of forming flash memory structures | 02-Mar-2010 |
| 28 |
US 7670898 B2
patent document
|
Methods of forming semiconductor constructions | 02-Mar-2010 |
| 29 |
US 7670646 B2
patent document
|
Methods for atomic-layer deposition | 02-Mar-2010 |
| 30 |
US 7670469 B2
patent document
|
Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals | 02-Mar-2010 |
| 31 |
US 7670466 B2
patent document
|
Methods and apparatuses for electrochemical-mechanical polishing | 02-Mar-2010 |
| 32 |
US 7669092 B2
patent document
|
Apparatus, method, and system of NAND defect management | 23-Feb-2010 |
| 33 |
US 7669064 B2
patent document
|
Diagnostic and managing distributed processor system | 23-Feb-2010 |
| 34 |
US 7669027 B2
patent document
|
Memory command delay balancing in a daisy-chained memory topology | 23-Feb-2010 |
| 35 |
US 7668893 B2
patent document
|
Data generator having linear feedback shift registers for generating data pattern in forward and reverse orders | 23-Feb-2010 |
| 36 |
US 7668012 B2
patent document
|
Memory cell programming | 23-Feb-2010 |
| 37 |
US 7668000 B2
patent document
|
Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance | 23-Feb-2010 |
| 38 |
US 7667632 B2
patent document
|
Quantizing circuits for semiconductor devices | 23-Feb-2010 |
| 39 |
US 7667260 B2
patent document
|
Nanoscale floating gate and methods of formation | 23-Feb-2010 |
| 40 |
US 7667258 B2
patent document
|
Double-sided container capacitors using a sacrificial layer | 23-Feb-2010 |
| 41 |
US 7667234 B2
patent document
|
High density memory array having increased channel widths | 23-Feb-2010 |
| 42 |
US 7666801 B2
patent document
|
Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands | 23-Feb-2010 |
| 43 |
US 7666797 B2
patent document
|
Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative to conductive material | 23-Feb-2010 |
| 44 |
US 7666788 B2
patent document
|
Methods for forming conductive vias in semiconductor device components | 23-Feb-2010 |
| 45 |
US 7666776 B2
patent document
|
Methods of forming conductive structures | 23-Feb-2010 |
| 46 |
US 7666578 B2
patent document
|
Efficient pitch multiplication process | 23-Feb-2010 |
| 47 |
US 7664999 B2
patent document
|
Real time testing using on die termination (ODT) circuit | 16-Feb-2010 |
| 48 |
US 7664216 B2
patent document
|
Digital frequency locked delay line | 16-Feb-2010 |
| 49 |
US 7663952 B2
patent document
|
Capacitor supported precharging of memory digit lines | 16-Feb-2010 |
| 50 |
US 7663934 B2
patent document
|
Program method with optimized voltage level for flash memory | 16-Feb-2010 |