Preparing your result...
Loading...
Press Esc to dismiss this message

Methods for atomic-layer deposition (02-Mar-2010)

Thumbnail
US Patent Publication (Source: USPTO)
Publication No. US 7670646 B2 published on 02-Mar-2010
Application No. US 11/620324 filed on 05-Jan-2007
Abstract (English)
Atomic-Layer deposition systems and methods provide a variety of electronic products. In an embodiment, a method uses an atomic-layer deposition system that includes an outer chamber, a substrate holder, and a gas-distribution fixture that engages or cooperates with the substrate holder to form an inner chamber within the outer chamber. The inner chamber has a smaller volume than the outer chamber, which leads to less time to fill and purge during cycle times for deposition of materials.
Inventors/Applicants
Ahn, Kie Y. [+1] [-1]
Chappaqua, NY, US
Forbes, Leonard
Corvallis, OR, US
Assignees
Micron Technology, Inc.
Boise, ID, US
Classifications
International (2006.01): C23C 16/00
National: 427/255.32; 427/255.7; 427/255.28; 427/294
Field of Search: 427/248.1; 427/569; 118/728.-732
Patent References
US 2501563 A Method of forming strongly adherent metallic compound films by glow discharge Mar-1950
US 3357961 A Copolymers of ethylene and hexadiene 1, 5 Dec-1967
US 3381114 A Device for manufacturing epitaxial crystals Apr-1968 [+1241] [-1241]
US 3407479 A Isolation of semiconductor devices Oct-1968
US 3457123 A Methods for making semiconductor structures having glass insulated islands Jul-1969
US 3471754 A Isolation structure for integrated circuits Oct-1969
US 3689357 A Glass-polysilicon dielectric isolation Sep-1972
US 4051354 A Fault-tolerant cell addressable array Sep-1977
US 4058430 A Method for producing compound thin films Nov-1977
US 4209357 A Plasma reactor apparatus Jun-1980
US 4215156 A Method for fabricating tantalum semiconductor contacts Jul-1980
US 4292093 A Method using laser irradiation for the production of atomically clean crystalline silicon and germanium surfaces Sep-1981
US 4305640 A Laser beam annealing diffuser Dec-1981
US 4333808 A Method for manufacture of ultra-thin film capacitor Jun-1982
US 4372032 A Normally off InP field effect transistor making process Feb-1983
US 4394673 A Rare earth silicide Schottky barriers Jul-1983
US 4399424 A Gas sensor Aug-1983
US 4413022 A Method for performing growth of compound thin films Nov-1983
US 4590042 A Plasma reactor having slotted manifold May-1986
US 4604162 A Formation and planarization of silicon-on-insulator structures Aug-1986
US 4608215 A Preparation of ceramics Aug-1986
US 4640871 A Magnetic material having high permeability in the high frequency range Feb-1987
US 4645622 A Electrically conductive ceramic material Feb-1987
US 4647947 A Optical protuberant bubble recording medium Mar-1987
US 4663831 A Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers May-1987
US 4673962 A Vertical DRAM cell and method Jun-1987
US 4693211 A Surface treatment apparatus Sep-1987
US 4725887 A Method of and apparatus for processing video signals Feb-1988
US 4749888 A Josephson transmission line device Jun-1988
US 4757360 A Floating gate memory device with facing asperities on floating and control gates Jul-1988
US 4761768 A Programmable logic device Aug-1988
US 4766569 A Programmable logic array Aug-1988
US 4767641 A Plasma treatment apparatus Aug-1988
US 4864375 A Dram cell and method Sep-1989
US 4870923 A Apparatus for treating the surfaces of wafers Oct-1989
US 4894801 A Stacked MOS transistor flip-flop memory cell Jan-1990
US 4896293 A Dynamic ram cell with isolated trench capacitors Jan-1990
US 4902533 A Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide Feb-1990
US 4920065 A Method of making ultra dense dram cells Apr-1990
US 4920071 A High temperature interconnect system for an integrated circuit Apr-1990
US 4920396 A CMOS having buried layer for carrier recombination Apr-1990
US 4926224 A Crosspoint dynamic ram cell for folded bitline array May-1990
US 4933743 A High performance interconnect system for an integrated circuit Jun-1990
US 4940636 A Optical interference filter Jul-1990
US 4947221 A Memory cell for a dense EPROM Aug-1990
US 4948937 A Apparatus and method for heat cleaning semiconductor material Aug-1990
US 4954854 A Cross-point lightly-doped drain-source trench transistor and fabrication process therefor Sep-1990
US 4958318 A Sidewall capacitor DRAM cell Sep-1990
US 4962476 A Semiconductor memory device having bit lines less liable to have influences of the adjacent bit lines Oct-1990
US 4962879 A Method for bubble-free bonding of silicon wafers Oct-1990
US 4975014 A High temperature low thermal expansion fastener Dec-1990
US 4987089 A BiCMOS process and process for forming bipolar transistors on wafers also containing FETs Jan-1991
US 4993358 A Chemical vapor deposition reactor and method of operation Feb-1991
US 5001526 A Dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof Mar-1991
US 5006192 A Apparatus for producing semiconductor devices Apr-1991
US 5006909 A Dram with a vertical capacitor and transistor Apr-1991
US 5010386 A Insulator separated vertical CMOS Apr-1991
US 5017504 A Vertical type MOS transistor and method of formation thereof May-1991
US 5019728 A High speed CMOS backpanel transceiver May-1991
US 5021355 A Method of fabricating cross-point lightly-doped drain-source trench transistor Jun-1991
US 5028977 A Merged bipolar and insulated gate transistors Jul-1991
US 5032545 A Process for preventing a native oxide from forming on the surface of a semiconductor material and integrated circuit capacitors produced thereby Jul-1991
US 5037773 A Stacked capacitor doping technique making use of rugged polysilicon Aug-1991
US 5049516 A Method of manufacturing semiconductor memory device Sep-1991
US 5053351 A Method of making stacked E-cell capacitor DRAM cell Oct-1991
US 5055319 A Controlled high rate deposition of metal oxide films Oct-1991
US 5057896 A Semiconductor device and method of producing same Oct-1991
US 5072269 A Dynamic ram and method of manufacturing the same Dec-1991
US 5075536 A Heating element assembly for glow plug Dec-1991
US 5080928 A Method for making moisture insensitive zinc sulfide based luminescent materials Jan-1992
US 5089084 A Hydrofluoric acid etcher and cascade rinser Feb-1992
US 5097291 A Energy amount control device Mar-1992
US 5102817 A Vertical DRAM cell and method Apr-1992
US 5110752 A Roughened polysilicon surface capacitor electrode plate for high denity dram May-1992
US 5119329 A Memory cell based on ferro-electric non volatile variable resistive element Jun-1992
US 5122848 A Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance Jun-1992
US 5122856 A Semiconductor device Jun-1992
US 5135879 A Method of fabricating a high density EPROM cell on a trench wall Aug-1992
US 5135889 A Method for forming a shielding structure for decoupling signal traces in a semiconductor Aug-1992
US 5149596 A Vapor deposition of thin films Sep-1992
US 5156987 A High performance thin film transistor (TFT) by solid phase epitaxial regrowth Oct-1992
US 5177028 A Trench isolation method having a double polysilicon gate formed on mesas Jan-1993
US 5177576 A Dynamic random access memory having trench capacitors and vertical transistors Jan-1993
US 5192704 A Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell Mar-1993
US 5198029 A Apparatus for coating small solids Mar-1993
US 5202278 A Method of forming a capacitor in semiconductor wafer processing Apr-1993
US 5208657 A DRAM Cell with trench capacitor and vertical channel in substrate May-1993
US 5216266 A Semiconductor memory device having memory cells formed in trench and manufacturing method therefor Jun-1993
US 5223001 A Vacuum processing apparatus Jun-1993
US 5223081 A Method for roughening a silicon or polysilicon surface for a semiconductor substrate Jun-1993
US 5223808 A Planar ferrite phase shifter Jun-1993
US 5229647 A High density data storage using stacked wafers Jul-1993
US 5234535 A Method of producing a thin silicon-on-insulator layer Aug-1993
US 5241211 A Semiconductor device Aug-1993
US 5254499 A Method of depositing high density titanium nitride films on semiconductor wafers Oct-1993
US 5266514 A Method for producing a roughened surface capacitor Nov-1993
US 5272367 A Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams) Dec-1993
US 5274249 A Superconducting field effect devices with thin channel layer Dec-1993
US 5302461 A Dielectric films for use in magnetoresistive transducers Apr-1994
US 5304622 A Process for producing polysilanes Apr-1994
US 5316962 A Method of producing a semiconductor device having trench capacitors and vertical switching transistors May-1994
US 5320880 A Method of providing a silicon film having a roughened outer surface Jun-1994
US 5324980 A Multi-layer type semiconductor device with semiconductor element layers stacked in opposite direction and manufacturing method thereof Jun-1994
US 5327380 A Method and apparatus for inhibiting a predecoder when selecting a redundant row line Jul-1994
US 5352998 A Microwave integrated circuit having a passive circuit substrate mounted on a semiconductor circuit substrate Oct-1994
US 5363550 A Method of Fabricating a micro-coaxial wiring structure Nov-1994
US 5365477 A Dynamic random access memory device Nov-1994
US 5376575 A Method of making dynamic random access memory having a vertical transistor Dec-1994
US 5379255 A Three dimensional famos memory devices and methods of fabricating Jan-1995
US 5382540 A Process for forming an electrically programmable read-only memory cell Jan-1995
US 5391911 A Reach-through isolation silicon-on-insulator device Feb-1995
US 5392245 A Redundancy elements using thin film transistors (TFTs) Feb-1995
US 5393704 A Self-aligned trenched contact (satc) process Feb-1995
US 5396093 A Vertical DRAM cross point memory cell and fabrication method Mar-1995
US 5410169 A Dynamic random access memory having bit lines buried in semiconductor substrate Apr-1995
US 5414287 A Process for high density split-gate memory cell for flash or EPROM May-1995
US 5414288 A Vertical transistor having an underlying gate electrode contact May-1995
US 5416041 A Method for producing an insulating trench in an SOI substrate May-1995
US 5421953 A Method and apparatus for direct bonding two bodies Jun-1995
US 5422499 A Sixteen megabit static random access memory (SRAM) cell Jun-1995
US 5426603 A Dynamic RAM and information processing system using the same Jun-1995
US 5427972 A Method of making a sidewall contact Jun-1995
US 5429966 A Method of fabricating a textured tunnel oxide for EEPROM applications Jul-1995
US 5432739 A Non-volatile sidewall memory cell method of fabricating same Jul-1995
US 5434878 A Optical gain medium having doped nanocrystals of semiconductors and also optical scatterers Jul-1995
US 5438009 A Method of fabrication of MOSFET device with buried bit line Aug-1995
US 5439524 A Plasma processing apparatus Aug-1995
US 5440158 A Electrically programmable memory device with improved dual floating gates Aug-1995
US 5441591 A Silicon to sapphire bond Aug-1995
US 5444013 A Method of forming a capacitor Aug-1995
US 5445699 A Processing apparatus with a gas distributor having back and forth parallel movement relative to a workpiece support surface Aug-1995
US 5445986 A Method of forming a roughened surface capacitor with two etching steps Aug-1995
US 5449433 A Use of a high density plasma source having an electrostatic shield for anisotropic polysilicon etching over topography Sep-1995
US 5450026 A Current mode driver for differential bus Sep-1995
US 5455445 A Multi-level semiconductor structures having environmentally isolated elements Oct-1995
US 5455489 A Displays comprising doped nanocrystal phosphors Oct-1995
US 5460316 A Stencils having enhanced wear-resistance and methods of manufacturing the same Oct-1995
US 5460988 A Process for high density flash EPROM cell Oct-1995
US 5466625 A Method of making a high-density DRAM structure on SOI Nov-1995
US 5483094 A Electrically programmable read-only memory cell Jan-1996
US 5483487 A Electrically programmable memory device with improved dual floating gates Jan-1996
US 5492853 A Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device Feb-1996
US 5495441 A Split-gate flash memory cell Feb-1996
US 5497017 A Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors Mar-1996
US 5504357 A Dynamic random access memory having a vertical transistor Apr-1996
US 5504376 A Stacked-type semiconductor device Apr-1996
US 5508219 A SOI DRAM with field-shield isolation and body contact Apr-1996
US 5508542 A Porous silicon trench and capacitor structures Apr-1996
US 5510758 A Multilayer microstrip wiring board with a semiconductor device mounted thereon via bumps Apr-1996
US 5516588 A Composite body, its use and a process for its production May-1996
US 5519236 A Semiconductor memory device having surrounding gate transistor May-1996
US 5521536 A Integrated circuit device having different signal transfer circuits for wirings with different lengths May-1996
US 5522932 A Corrosion-resistant apparatus Jun-1996
US 5523261 A Method of cleaning high density inductively coupled plasma chamber using capacitive coupling Jun-1996
US 5528062 A High-density DRAM structure on soi Jun-1996
US 5562952 A Plasma-CVD method and apparatus Oct-1996
US 5563083 A Method of fabricating non-volatile sidewall memory cell Oct-1996
US 5572052 A Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer Nov-1996
US 5574299 A Semiconductor device having vertical conduction transistors and cylindrical cell gates Nov-1996
US 5585020 A Process for the production of nanoparticles Dec-1996
US 5587609 A II-VI group compound semiconductor device metallic nitride ohmic contact for p-type Dec-1996
US 5593912 A SOI trench DRAM cell for 256 MB DRAM and beyond Jan-1997
US 5595606 A Shower head and film forming apparatus using the same Jan-1997
US 5599396 A High density inductively and capacitively coupled plasma chamber Feb-1997
US 5614026 A Showerhead for uniform distribution of process gas Mar-1997
US 5616934 A Fully planarized thin film transistor (TFT) and process to fabricate same Apr-1997
US 5619159 A Signal processing device and a method for transmitting signal Apr-1997
US 5621681 A Device and manufacturing method for a ferroelectric memory Apr-1997
US 5625233 A Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum oxide Apr-1997
US 5636170 A Low voltage dynamic memory Jun-1997
US 5640342 A Structure for cross coupled thin film transistors and static random access memory cell Jun-1997
US 5644540 A Redundancy elements using thin film transistors (TFTs) Jul-1997
US 5646900 A Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device Jul-1997
US 5652061 A Devices comprising films of .beta.-C3 N4 Jul-1997
US 5656548 A Method for forming three dimensional processor using transferred thin film circuits Aug-1997
US 5662834 A Alloys of Ti Ru Fe and O and use thereof for the manufacture of cathodes for the electrochemical synthesis of sodium chlorate Sep-1997
US 5674563 A Method for ferroelectric thin film production Oct-1997
US 5674574 A Vapor delivery system for solid precursors and method regarding same Oct-1997
US 5691230 A Technique for producing small islands of silicon on insulator Nov-1997
US 5696008 A Semiconductor device and method of manufacturing the same Dec-1997
US 5698022 A Lanthanide/phosphorus precursor compositions for MOCVD of lanthanide/phosphorus oxide films Dec-1997
US 5705415 A Process for forming an electrically programmable read-only memory cell Jan-1998
US 5710057 A SOI fabrication method Jan-1998
US 5714336 A Process and test kit for determining free active compounds in biological fluids Feb-1998
US 5714766 A Nano-structure memory device Feb-1998
US 5729047 A Method and structure for providing signal isolation and decoupling in an integrated circuit device Mar-1998
US 5735960 A Apparatus and method to increase gas residence time in a reactor Apr-1998
US 5739524 A Dynamic distance and position sensor and method of measuring the distance and the position of a surface using a sensor of this kind Apr-1998
US 5744374 A Device and manufacturing method for a ferroelectric memory Apr-1998
US 5745334 A Capacitor formed within printed circuit board Apr-1998
US 5751021 A Semiconductor light-emitting device May-1998
US 5756404 A Two-step nitride deposition May-1998
US 5757044 A Electrically erasable and programmable read only memory cell with split floating gate for preventing cell from over-erase May-1998
US 5765214 A Memory access method and apparatus and multi-plane memory device with prefetch Jun-1998
US 5770022 A Method of making silica nanoparticles Jun-1998
US 5772153 A Aircraft icing sensors Jun-1998
US 5772760 A Method for the preparation of nanocrystalline diamond thin films Jun-1998
US 5789030 A Method for depositing doped amorphous or polycrystalline silicon on a substrate Aug-1998
US 5792269 A Gas distribution for CVD systems Aug-1998
US 5795808 A Method for forming shallow junction for semiconductor device Aug-1998
US 5801105 A Multilayer thin film, substrate for electronic device, electronic device, and preparation of multilayer oxide thin film Sep-1998
US 5810923 A Method for forming oxide thin film and the treatment of silicon substrate Sep-1998
US 5811984 A Current mode I/O for digital circuits Sep-1998
US 5822256 A Method and circuitry for usage of partially functional nonvolatile memory Oct-1998
US 5827571 A Hot-wall CVD method for forming a ferroelectric film Oct-1998
US 5828080 A Oxide thin film, electronic device substrate and electronic device Oct-1998
US 5840897 A Metal complex source reagents for chemical vapor deposition Nov-1998
US 5851880 A Method of making nonvolatile memory elements with selector transistors Dec-1998
US 5869369 A Method of fabricating a flash memory Feb-1999
US 5874134 A Production of nanostructured materials by hypersonic plasma particle deposition Feb-1999
US 5874760 A 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation Feb-1999
US 5879459 A Vertically-stacked process reactor and cluster tool system for atomic layer deposition Mar-1999
US 5880601 A Signal receiving circuit and digital signal processing system Mar-1999
US 5882779 A Semiconductor nanocrystal display materials and display apparatus employing same Mar-1999
US 5885864 A Method for forming compact memory cell using vertical devices Mar-1999
US 5888868 A Method for fabricating EPROM device Mar-1999
US 5891773 A Non-volatile semiconductor storage apparatus and production thereof Apr-1999
US 5892249 A Integrated circuit having reprogramming cell Apr-1999
US 5907170 A Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor May-1999
US 5909618 A Method of making memory cell with vertical transistor and buried word and body lines Jun-1999
US 5910684 A Integrated circuitry Jun-1999
US 5910880 A Semiconductor circuit components and capacitors Jun-1999
US 5912797 A Dielectric materials of amorphous compositions and devices employing same Jun-1999
US 5916365 A Sequential chemical vapor deposition Jun-1999
US 5923056 A Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials Jul-1999
US 5936274 A High density flash memory Aug-1999
US 5939146 A Method for thermal spraying of nanocrystalline coatings and materials for the same Aug-1999
US 5950925 A Reactant gas ejector head Sep-1999
US 5952039 A Method for manufacturing DRAM capacitor Sep-1999
US 5958140 A One-by-one type heat-processing apparatus Sep-1999
US 5962132 A Silica nanoparticles obtained from a method involving a direct current electric arc in an oxygen-containing atmosphere Oct-1999
US 5963833 A Method for cleaning semiconductor wafers and Oct-1999
US 5972847 A Method for making high-critical-current-density YBa2 Cu3 O7 superconducting layers on metallic substrates Oct-1999
US 5973352 A Ultra high density flash memory having vertically stacked devices Oct-1999
US 5973356 A Ultra high density flash memory Oct-1999
US 5981350 A Method for forming high capacitance memory cells Nov-1999
US 5989511 A Smooth diamond films as low friction, long wear surfaces Nov-1999
US 5990605 A Electron emission device and display device using the same Nov-1999
US 5991225 A Programmable memory address decode array with vertical transistors Nov-1999
US 5994240 A Method for cleaning semiconductor wafers Nov-1999
US 5998528 A Viscous carrier compositions, including gels, formed with an organic liquid carrier, a layered material: polymer complex, and a di-, and/or tri-valent cation Dec-1999
US 6010969 A Method of depositing films on semiconductor devices by using carboxylate complexes Jan-2000
US 6013548 A Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array Jan-2000
US 6013553 A Zirconium and/or hafnium oxynitride gate dielectric Jan-2000
US 6017820 A Integrated vacuum and plating cluster system Jan-2000
US 6019848 A Lid assembly for high temperature processing chamber Feb-2000
US 6020024 A Method for forming high dielectric constant metal oxides Feb-2000
US 6020243 A Zirconium and/or hafnium silicon-oxynitride gate dielectric Feb-2000
US 6022787 A Method of making a structure for providing signal isolation and decoupling in an integrated circuit device Feb-2000
US 6023124 A Electron emission device and display device using the same Feb-2000
US 6023125 A Electron emission device and display using the same Feb-2000
US 6025034 A Method of manufacture of nanostructured feeds Feb-2000
US 6025225 A Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same Feb-2000
US 6025627 A Alternate method and structure for improved floating gate tunneling devices Feb-2000
US 6027960 A Laser annealing method and laser annealing device Feb-2000
US 6027961 A CMOS semiconductor devices and method of formation Feb-2000
US 6034015 A Ceramic compositions for microwave wireless communication Mar-2000
US 6034389 A Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array Mar-2000
US 6040218 A Two square NVRAM cell Mar-2000
US 6040243 A Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion Mar-2000
US 6057271 A Method of making a superconducting microwave component by off-axis sputtering May-2000
US 6059885 A Vapor deposition apparatus and method for forming thin film May-2000
US 6060743 A Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same May-2000
US 6060755 A Aluminum-doped zirconium dielectric film transistor structure and deposition method for same May-2000
US 6063705 A Precursor chemistries for chemical vapor deposition of ruthenium and ruthenium oxide May-2000
US 6066869 A Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor May-2000
US 6072209 A Four F2 folded bit line DRAM cell structure having buried bit and word lines Jun-2000
US 6075383 A GTL output amplifier for coupling an input signal present at the input into a transmission line present at the output Jun-2000
US 6075691 A Thin film capacitors and process for making them Jun-2000
US 6077745 A Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array Jun-2000
US RE36760 E Method and apparatus for altering material using ion beams Jul-2000
US 6083793 A Method to manufacture nonvolatile memories with a trench-pillar cell structure for high capacitive coupling ratio Jul-2000
US 6090636 A Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same Jul-2000
US 6093623 A Methods for making silicon-on-insulator structures Jul-2000
US 6093944 A Dielectric materials of amorphous compositions of TI-O2 doped with rare earth elements and devices employing same Jul-2000
US 6103419 A Solid secondary lithium cell based on lithiated zirconium, titanium or hafnium oxide cathode material Aug-2000
US 6104061 A Memory cell with vertical transistor and buried word and body lines Aug-2000
US 6110529 A Method of forming metal films on a substrate by chemical vapor deposition Aug-2000
US 6111285 A Boride electrodes and barriers for cell dielectrics Aug-2000
US 6114252 A Plasma processing tools, dual-source plasma etchers, dual-source plasma etching methods, and methods of forming planar coil dual-source plasma etchers Sep-2000
US 6114725 A Structure for folded architecture pillar memory cell Sep-2000
US 6115401 A External cavity semiconductor laser with monolithic prism assembly Sep-2000
US 6120531 A Physiotherapy fiber, shoes, fabric, and clothes utilizing electromagnetic energy Sep-2000
US 6124729 A Field programmable logic arrays with vertical transistors Sep-2000
US 6125062 A Single electron MOSFET memory device and method Sep-2000
US 6127287 A Silicon nitride deposition method for use in forming a memory cell dielectric Oct-2000
US 6129928 A Biomimetic calcium phosphate implant coatings and methods for making the same Oct-2000
US 6130503 A Electron emission device and display using the same Oct-2000
US 6133621 A Integrated shielded electric connection Oct-2000
US 6134175 A Memory address decode array with vertical transistors Oct-2000
US 6137025 A Ceramic composition for immobilization of actinides Oct-2000
US 6140181 A Memory using insulator traps Oct-2000
US 6141238 A Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including same Oct-2000
US 6141260 A Single electron resistor memory device and method for use thereof Oct-2000
US 6143582 A High density electronic circuit modules Nov-2000
US 6143616 A Methods of forming coaxial integrated circuitry interconnect lines Nov-2000
US 6143636 A High density flash memory Nov-2000
US 6144155 A Electron emission device and display device using the same Nov-2000
US 6146959 A Method of forming capacitors containing tantalum Nov-2000
US 6146976 A Method for producing bridged doped zones Nov-2000
US 6147443 A Electron emission device and display device using the same Nov-2000
US 6150188 A Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same Nov-2000
US 6150687 A Memory cell having a vertical transistor with buried source/drain and dual gates Nov-2000
US 6150724 A Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces Nov-2000
US 6153468 A Method of forming a logic array for a decoder Nov-2000
US 6154280 A System and method for measuring the microroughness of a surface of a substrate Nov-2000
US H1924 H Load-adaptive nanocrystalline carbon/amorphous diamond-like carbon composite and preparation method Dec-2000
US 6161500 A Apparatus and method for preventing the premature mixture of reactant gases in CVD and PECVD reactions Dec-2000
US 6162712 A Platinum source compositions for chemical vapor deposition of platinum Dec-2000
US 6165837 A Semiconductor integrated memory manufacturing method and device Dec-2000
US 6166487 A Electron emission device and display device using the same Dec-2000
US 6171900 B1 CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET Jan-2001
US 6174784 B1 Technique for producing small islands of silicon on insulator Jan-2001
US 6174809 B1 Method for forming metal layer using atomic layer deposition Jan-2001
US 6184146 B1 Plasma producing tools, dual-source plasma etchers, dual-source plasma etching methods, and method of forming planar coil dual-source plasma etchers Feb-2001
US 6184549 B1 Trench storage dynamic random access memory cell with vertical transfer device Feb-2001
US 6184550 B1 Ternary nitride-carbide barrier layers Feb-2001
US 6184612 B1 Electron emission device with electron supply layer of hydrogenated amorphous silicon Feb-2001
US 6187484 B1 Irradiation mask Feb-2001
US 6191443 B1 Capacitors, methods of forming capacitors, and DRAM memory cells Feb-2001
US 6191448 B1 Memory cell with vertical transistor and buried word and body lines Feb-2001
US 6191470 B1 Semiconductor-on-insulator memory cell with buried word and body lines Feb-2001
US 6194237 B1 Method for forming quantum dot in semiconductor device and a semiconductor device resulting therefrom Feb-2001
US 6194262 B1 Method for coupling to semiconductor device in an integrated circuit having edge-defined, sub-lithographic conductors Feb-2001
US 6198168 B1 Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same Mar-2001
US 6200893 B1 Radical-assisted sequential CVD Mar-2001
US 6203613 B1 Atomic layer deposition with nitrate containing precursors Mar-2001
US 6203726 B1 Phosphor Materials Mar-2001
US 6206972 B1 Method and apparatus for providing uniform gas delivery to substrates in CVD and PECVD processes Mar-2001
US 6207522 B1 Formation of thin film capacitors Mar-2001
US 6207589 B1 Method of forming a doped metal oxide dielectric film Mar-2001
US 6208164 B1 Programmable logic array with vertical transistors Mar-2001
US 6208881 B1 Catheter with thin film electrodes and method for making same Mar-2001
US 6210999 B1 Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices Apr-2001
US 6211015 B1 Ultra high density flash memory having vertically stacked devices Apr-2001
US 6211035 B1 Integrated circuit and method Apr-2001
US 6211039 B1 Silicon-on-insulator islands and method for their formation Apr-2001
US 6217645 B1 Method of depositing films by using carboxylate complexes Apr-2001
US 6218293 B1 Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride Apr-2001
US 6219299 B1 Programmable memory decode circuits with transistors with vertical gates Apr-2001
US 6222788 B1 Vertical gate transistors in pass transistor logic decode circuits Apr-2001
US 6224690 B1 Flip-Chip interconnections using lead-free solders May-2001
US 6225168 B1 Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof May-2001
US 6225237 B1 Method for forming metal-containing films using metal complexes with chelating O- and/or N-donor ligands May-2001
US 6226599 B1 Electromagnetic wave analyzer apparatus May-2001
US 6230651 B1 Gas injection system for plasma processing May-2001
US 6232643 B1 Memory using insulator traps May-2001
US 6232847 B1 Trimmable singleband and tunable multiband integrated oscillator using micro-electromechanical system (MEMS) technology May-2001
US 6238976 B1 Method for forming high density flash memory May-2001
US 6246606 B1 Memory using insulator traps Jun-2001
US 6249460 B1 Dynamic flash memory cells with ultrathin tunnel oxides Jun-2001
US 6252267 B1 Five square folded-bitline DRAM cell Jun-2001
US 6255852 B1 Current mode signal interconnects and CMOS amplifier Jul-2001
US 6258637 B1 Method for thin film deposition on single-crystal semiconductor substrates Jul-2001
US 6259198 B1 Flat panel display apparatus with an array of electron emitting devices Jul-2001
US 6270835 B1 Formation of this film capacitors Aug-2001
US 6273951 B1 Precursor mixtures for use in preparing layers on substrates Aug-2001
US 6274479 B1 Flowable germanium doped silicate glass for use as a spacer oxide Aug-2001
US 6274937 B1 Silicon multi-chip module packaging with integrated passive components and method of making Aug-2001
US 6277448 B2 Thermal spray method for the formation of nanostructured coatings Aug-2001
US 6278230 B1 Electron emission device and display device using the same Aug-2001
US 6281042 B1 Structure and method for a high performance electronic packaging assembly Aug-2001
US 6281054 B1 SOI device and method for fabricating the same Aug-2001
US 6281144 B1 Exclusion of polymer film from semiconductor wafer edge and backside during film (CVD) deposition Aug-2001
US 6282080 B1 Semiconductor circuit components and capacitors Aug-2001
US 6285123 B1 Electron emission device with specific island-like regions Sep-2001
US 6289842 B1 Plasma enhanced chemical vapor deposition system Sep-2001
US 6290491 B1 Method for heating a semiconductor wafer in a process chamber by a shower head, and process chamber Sep-2001 432/5
US 6291314 B1 Controlled cleavage process and device for patterned films using a release layer Sep-2001
US 6291341 B1 Method for PECVD deposition of selected material films Sep-2001
US 6291364 B1 Method and apparatus for stabilizing high pressure oxidation of a semiconductor device Sep-2001
US 6291866 B1 Zirconium and/or hafnium oxynitride gate dielectric Sep-2001
US 6294813 B1 Information handling system having improved floating gate tunneling devices Sep-2001
US 6296943 B1 Method for producing composite sol, coating composition, and optical element Oct-2001
US 6297095 B1 Memory device that includes passivated nanoclusters and method for manufacture Oct-2001
US 6297103 B1 Structure and method for dual gate oxide thicknesses Oct-2001
US 6297516 B1 Method for deposition and patterning of organic thin film Oct-2001
US 6297527 B1 Multilayer electrode for ferroelectric and high dielectric constant capacitors Oct-2001
US 6297539 B1 Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same Oct-2001
US 6300203 B1 Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors Oct-2001
US 6300255 B1 Method and apparatus for processing semiconductive wafers Oct-2001
US 6302964 B1 One-piece dual gas faceplate for a showerhead in a semiconductor wafer processing system Oct-2001
US 6303481 B2 Method for forming a gate insulating film for semiconductor devices Oct-2001
US 6303500 B1 Method and apparatus for electroless plating a contact pad Oct-2001
US 6313015 B1 Growth method for silicon nanowires and nanoparticle chains from silicon monoxide Nov-2001
US 6313035 B1 Chemical vapor deposition using organometallic precursors Nov-2001
US 6313518 B1 Porous silicon oxycarbide integrated circuit insulator Nov-2001
US 6313531 B1 Coaxial integrated circuitry interconnect lines, and integrated circuitry Nov-2001
US 6316800 B1 Boride electrodes and barriers for cell dielectrics Nov-2001
US 6316873 B1 Electron emission device and display device using the same Nov-2001
US 6317175 B1 Single crystal silicon arrayed devices with optical shield between transistor and substrate Nov-2001
US 6317357 B1 Vertical bipolar read access for low voltage memory cell Nov-2001
US 6320091 B1 Process for making a ceramic composition for immobilization of actinides Nov-2001
US 6331282 B1 Manganese oxyiodides and their method of preparation and use in energy storage Dec-2001
US 6331465 B1 Alternate method and structure for improved floating gate tunneling devices using textured surface Dec-2001
US 6337805 B1 Discrete devices including EAPROM transistor and NVRAM memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatuses including same Jan-2002
US 6342445 B1 Method for fabricating an SrRuO3 film Jan-2002
US 6346477 B1 Method of interlayer mediated epitaxy of cobalt silicide from low temperature chemical vapor deposition of cobalt Feb-2002
US 6347749 B1 Semiconductor processing reactor controllable gas jet assembly Feb-2002
US 6348386 B1 Method for making a hafnium-based insulating film Feb-2002
US 6348709 B1 Electrical contact for high dielectric constant capacitors and method for fabricating the same Feb-2002
US 6350649 B1 Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof Feb-2002
US 6350704 B1 Porous silicon oxycarbide integrated circuit insulator Feb-2002
US 6351411 B2 Memory using insulator traps Feb-2002
US 6352591 B1 Methods and apparatus for shallow trench isolation Mar-2002
US 6355561 B1 ALD method to improve surface coverage Mar-2002
US 6365470 B1 Method for manufacturing self-matching transistor Apr-2002
US 6365519 B2 Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride Apr-2002
US 6368398 B2 Method of depositing films by using carboxylate complexes Apr-2002
US 6368518 B1 Methods for removing rhodium- and iridium-containing films Apr-2002
US 6368941 B1 Fabrication of a shallow trench isolation by plasma oxidation Apr-2002
US 6373740 B1 Transmission lines for CMOS integrated circuits Apr-2002
US 6377070 B1 In-service programmable logic arrays with ultra thin vertical body transistors Apr-2002
US 6380579 B1 Capacitor of semiconductor device Apr-2002
US 6380765 B1 Double pass transistor logic with vertical gate transistors Apr-2002
US 6381124 B1 Handheld computer system Apr-2002
US 6381168 B2 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device Apr-2002
US 6387712 B1 Process for preparing ferroelectric thin films May-2002
US 6388376 B1 Electron emission device with electron supply layer having reduced resistance May-2002
US 6391769 B1 Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby May-2002
US 6392257 B1 Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same May-2002
US 6395650 B1 Methods for forming metal oxide layers with enhanced purity May-2002
US 6399979 B1 Memory cell having a vertical transistor with buried source/drain and dual gates Jun-2002
US 6400070 B1 Electron emission device and display device using the same Jun-2002
US 6400552 B2 Capacitor with conductively doped Si-Ge alloy electrode Jun-2002
US 6403494 B1 Method of forming a floating gate self-aligned to STI on EEPROM Jun-2002
US 6404027 B1 High dielectric constant gate oxides for silicon-based devices Jun-2002
US 6404124 B1 Electron emission device and display apparatus using the same Jun-2002
US 6407435 B1 Multilayer dielectric stack and method Jun-2002
US 6414476 B2 Current detecting device, impedance measuring instrument and power measuring instrument Jul-2002
US 6414543 B1 Rectifying charge storage element Jul-2002
US 6417537 B1 Metal oxynitride capacitor barrier layer Jul-2002
US 6418050 B2 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device Jul-2002
US 6420230 B1 Capacitor fabrication methods and capacitor constructions Jul-2002
US 6420279 B1 Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate Jul-2002
US 6420778 B1 Differential electrical transmission line structures employing crosstalk compensation and related methods Jul-2002
US 6423613 B1 Low temperature silicon wafer bond process with bulk material bond strength Jul-2002
US 6423649 B2 Method and apparatus for stabilizing high pressure oxidation of a semiconductor device Jul-2002
US 6424001 B1 Flash memory with ultra thin vertical body transistors Jul-2002
US 6429065 B2 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device Aug-2002
US 6432779 B1 Selective removal of a metal oxide dielectric Aug-2002
US 6433408 B1 Highly integrated circuit including transmission lines which have excellent characteristics Aug-2002
US 6433993 B1 Formation of thin film capacitors Aug-2002
US 6434041 B2 Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device Aug-2002
US 6436203 B1 CVD apparatus and CVD method Aug-2002
US 6437389 B1 Vertical gate transistors in pass transistor programmable logic arrays Aug-2002
US 6441417 B1 Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same Aug-2002
US 6444039 B1 Three-dimensional showerhead apparatus Sep-2002
US 6444042 B1 Gas injection system for chemical vapor deposition device Sep-2002
US 6444592 B1 Interfacial oxidation process for high-k gate dielectric process integration Sep-2002
US 6444895 B1 Device and method for nondestructive inspection on semiconductor device Sep-2002
US 6445023 B1 Mixed metal nitride and boride barrier layers Sep-2002
US 6447764 B1 Method for isolating anionic organic substances from aqueous systems using cationic polymer nanoparticles Sep-2002
US 6447848 B1 Nanosize particle coatings made by thermally spraying solution precursor feedstocks Sep-2002
US 6448192 B1 Method for forming a high dielectric constant material Sep-2002
US 6448601 B1 Memory address and decode circuits with ultra thin body transistors Sep-2002
US 6451641 B1 Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material Sep-2002
US 6451662 B1 Method of forming low-leakage on-chip capacitor Sep-2002
US 6451695 B2 Radical-assisted sequential CVD Sep-2002
US 6452229 B1 Ultra-thin fully depleted SOI device with T-shaped gate and method of fabrication Sep-2002
US 6454912 B1 Method and apparatus for the fabrication of ferroelectric films Sep-2002
US 6455717 B1 Metal complexes with chelating O-and/or N-donor ligands Sep-2002
US 6456535 B2 Dynamic flash memory cells with ultra thin tunnel oxides Sep-2002
US 6458431 B2 Methods for the lithographic deposition of materials containing nanoparticles Oct-2002
US 6458645 B2 Capacitor having tantalum oxynitride film and method for making same Oct-2002
US 6458701 B1 Method for forming metal layer of semiconductor device using metal halide gas Oct-2002
US 6461436 B1 Apparatus and process of improving atomic layer deposition chamber performance Oct-2002
US 6461914 B1 Process for making a MIM capacitor Oct-2002
US 6461970 B1 Method of reducing defects in anti-reflective coatings and semiconductor structures fabricated thereby Oct-2002
US 6465298 B2 Method of fabricating a semiconductor-on-insulator memory cell with buried word and body lines Oct-2002
US 6465334 B1 Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors Oct-2002
US 6465853 B1 Method for making semiconductor device Oct-2002
US 6472321 B2 Chemical vapor deposition process Oct-2002
US 6472632 B1 Method and apparatus for direct electrothermal-physical conversion of ceramic into nanopowder Oct-2002
US 6472702 B1 Deep trench DRAM with SOI and STI Oct-2002
US 6472803 B1 Electron emission light-emitting device and display apparatus using the same Oct-2002
US 6476434 B1 4 F2 folded bit line dram cell structure having buried bit and word lines Nov-2002
US 6482740 B2 Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH Nov-2002
US 6486027 B1 Field programmable logic arrays with vertical transistors Nov-2002
US 6486703 B2 Programmable logic array with vertical transistors Nov-2002
US 6489648 B2 Semiconductor device Dec-2002
US 6492233 B2 Memory cell with vertical transistor and buried word and body lines Dec-2002
US 6492241 B1 Integrated capacitors fabricated with conductive metal oxides Dec-2002
US 6492288 B2 Glass ceramic and temperature compensating member Dec-2002
US 6495436 B2 Formation of metal oxide gate dielectric Dec-2002
US 6496034 B2 Programmable logic arrays with ultra thin body transistors Dec-2002
US 6498063 B1 Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth Dec-2002
US 6498065 B1 Memory address decode array with vertical transistors Dec-2002
US 6504214 B1 MOSFET device having high-K dielectric layer Jan-2003
US 6506666 B2 Method of fabricating an SrRuO3 film Jan-2003
US 6509280 B2 Method for forming a dielectric layer of a semiconductor device Jan-2003
US 6514348 B2 Substrate processing apparatus Feb-2003
US 6514820 B2 Method for forming single electron resistor memory Feb-2003
US 6514828 B2 Method of fabricating a highly reliable gate oxide Feb-2003
US 6515510 B2 Programmable logic array with vertical transistors Feb-2003
US 6518121 B2 Boride electrodes and barriers for cell dielectrics Feb-2003
US 6518610 B2 Rhodium-rich oxygen barriers Feb-2003
US 6518615 B1 Method and structure for high capacitance memory cells Feb-2003
US 6518634 B1 Strontium nitride or strontium oxynitride gate dielectric Feb-2003
US 6521911 B2 High dielectric constant metal silicates formed by controlled metal-surface reactions Feb-2003
US 6524867 B2 Method for forming platinum-rhodium stack as an oxygen barrier Feb-2003
US 6524901 B1 Method for forming a notched damascene planar poly/metal gate Feb-2003
US 6526191 B1 Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same Feb-2003
US 6527866 B1 Apparatus and method for deposition of thin films Mar-2003
US 6531354 B2 Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors Mar-2003
US 6531727 B2 Open bit line DRAM with ultra thin body transistors Mar-2003
US 6533867 B2 Surface sealing showerhead for vapor deposition reactor having integrated flow diverters Mar-2003
US 6534357 B1 Methods for forming conductive structures and structures regarding same Mar-2003
US 6534420 B2 Methods for forming dielectric materials and methods for forming semiconductor devices Mar-2003
US 6537613 B1 Process for metal metalloid oxides and nitrides with compositional gradients Mar-2003
US 6538330 B1 Multilevel semiconductor-on-insulator structures and circuits Mar-2003
US 6540214 B2 Coil spring assembly Apr-2003
US 6541079 B1 Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique Apr-2003
US 6541280 B2 High K dielectric film Apr-2003
US 6541353 B1 Atomic layer doping apparatus and method Apr-2003
US 6544846 B2 Method of manufacturing a single electron resistor memory device Apr-2003
US 6544875 B1 Chemical vapor deposition of silicate high dielectric constant materials Apr-2003
US 6545314 B2 Memory using insulator traps Apr-2003
US 6545338 B1 Methods for implementing co-axial interconnect lines in a CMOS process for high speed RF and microwave applications Apr-2003
US 6551893 B1 Atomic layer deposition of capacitor dielectric Apr-2003
US 6551929 B1 Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques Apr-2003
US 6552383 B2 Integrated decoupling capacitors Apr-2003
US 6555858 B1 Self-aligned magnetic clad write line and its method of formation Apr-2003
US 6559014 B1 Preparation of composite high-K / standard-K dielectrics for semiconductor devices May-2003
US 6559472 B2 Film composition May-2003
US 6559491 B2 Folded bit line DRAM with ultra thin body transistors May-2003
US 6566147 B2 Method for controlling deposition of dielectric films May-2003
US 6566682 B2 Programmable memory address and decode circuits with ultra thin vertical body transistors May-2003
US 6569757 B1 Methods for forming co-axial interconnect lines in a CMOS process for high speed applications May-2003
US 6570248 B1 Structure and method for a high-performance electronic packaging assembly May-2003
US 6572836 B1 Method for producing gaseous hydrogen by chemical reaction of metals or metal hydrides subjected to intense mechanical deformations Jun-2003
US 6573199 B2 Methods of treating dielectric materials with oxygen, and methods of forming capacitor constructions Jun-2003
US 6580124 B1 Multigate semiconductor device with vertical channel current and method of fabrication Jun-2003
US 6586349 B1 Integrated process for fabrication of graded composite dielectric material layers for semiconductor devices Jul-2003
US 6586785 B2 Aerosol silicon nanoparticles for use in semiconductor device fabrication Jul-2003
US 6586792 B2 Structures, methods, and systems for ferroelectric memory transistors Jul-2003
US 6586797 B2 Graded composition gate insulators to reduce tunneling barriers in flash memory devices Jul-2003
US 6587408 B1 High-density mechanical memory and turing machine Jul-2003
US 6590252 B2 Semiconductor device with oxygen diffusion barrier layer termed from composite nitride Jul-2003
US 6592661 B1 Method for processing wafers in a semiconductor fabrication system Jul-2003
US 6592839 B2 Tailoring nanocrystalline diamond film properties Jul-2003
US 6592942 B1 Method for vapour deposition of a film onto a substrate Jul-2003
US 6593610 B2 Memory cell arrays Jul-2003
US 6596583 B2 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers Jul-2003
US 6596636 B2 ALD method to improve surface coverage Jul-2003
US 6597037 B1 Programmable memory address decode array with vertical transistors Jul-2003
US 6600339 B2 Current mode signal interconnects and CMOS amplifier Jul-2003
US 6602053 B2 Cooling structure and method of manufacturing the same Aug-2003
US 6602338 B2 Titanium dioxide film co-doped with yttrium and erbium and method for producing the same Aug-2003
US 6608378 B2 Formation of metal oxide gate dielectric Aug-2003
US 6613656 B2 Sequential pulse deposition Sep-2003
US 6613695 B2 Surface preparation prior to deposition Sep-2003
US 6613702 B2 Methods of forming capacitor constructions Sep-2003
US 6617634 B2 RuSixOy-containing adhesion layers and process for fabricating the same Sep-2003
US 6620670 B2 Process conditions and precursors for atomic layer deposition (ALD) of AL2O3 Sep-2003
US 6620752 B2 Method for fabrication of lead-based perovskite materials Sep-2003
US 6627260 B2 Deposition methods Sep-2003
US 6627503 B2 Method of forming a multilayer dielectric stack Sep-2003
US 6627508 B1 Method of forming capacitors containing tantalum Sep-2003
US 6630713 B2 Low temperature silicon wafer bond process with bulk material bond strength Oct-2003
US 6632279 B1 Method for growing thin oxide films Oct-2003
US 6638575 B1 Plasma sprayed oxygen transport membrane coatings Oct-2003
US 6638810 B2 Tantalum nitride CVD deposition by tantalum oxide densification Oct-2003
US 6638859 B2 Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition Oct-2003
US 6639267 B2 Capacitor dielectric having perovskite-type crystalline structure Oct-2003
US 6639268 B2 Flash memory with ultra thin vertical body transistors Oct-2003
US 6641887 B2 Optical recording medium Nov-2003
US 6642567 B1 Devices containing zirconium-platinum-containing materials and methods for preparing such materials and devices Nov-2003
US 6642573 B1 Use of high-K dielectric material in modified ONO structure for semiconductor devices Nov-2003
US 6645569 B2 Method of applying nanoparticles Nov-2003
US 6645882 B1 Preparation of composite high-K/standard-K dielectrics for semiconductor devices Nov-2003
US 6652924 B2 Sequential chemical vapor deposition Nov-2003
US 6653209 B1 Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device Nov-2003
US 6653591 B1 Method and apparatus for direct electrothermal-physical conversion of ceramic into nanopowder Nov-2003
US 6656371 B2 Methods of forming magnetoresisitive devices Dec-2003
US 6656792 B2 Nanocrystal flash memory device and manufacturing method therefor Dec-2003
US 6656835 B2 Process for low temperature atomic layer deposition of Rh Dec-2003
US 6660660 B2 Methods for making a dielectric stack in an integrated circuit Dec-2003
US 6661058 B2 Highly reliable gate oxide and method of fabrication Dec-2003
US 6664806 B2 Memory address and decode circuits with ultra thin body transistors Dec-2003
US 6669996 B2 Method of synthesizing metal doped diamond-like carbon films Dec-2003
US 6670284 B2 Method of decontaminating process chambers, methods of reducing defects in anti-reflective coatings, and resulting semiconductor structures Dec-2003
US 6673701 B1 Atomic layer deposition methods Jan-2004
US 6674138 B1 Use of high-k dielectric materials in modified ONO structure for semiconductor devices Jan-2004
US 6677250 B2 CVD apparatuses and methods of forming a layer over a semiconductor substrate Jan-2004
US 6677640 B1 Memory cell with tight coupling Jan-2004
US 6682602 B2 Chemical vapor deposition systems including metal complexes with chelating O- and/or N-donor ligands Jan-2004
US 6682969 B1 Top electrode in a strongly oxidizing environment Jan-2004
US 6683005 B2 Method of forming capacitor constructions Jan-2004
US 6683011 B2 Process for forming hafnium oxide films Jan-2004
US 6686212 B1 Method to deposit a stacked high-κ gate dielectric for CMOS applications Feb-2004
US 6689192 B1 Method for producing metallic nanoparticles Feb-2004
US 6689660 B1 4 F2 folded bit line DRAM cell structure having buried bit and word lines Feb-2004
US 6692898 B2 Self-aligned conductive line for cross-point magnetic memory integrated circuits Feb-2004
US 6696332 B2 Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing Feb-2004
US 6696724 B2 Two-transistor flash cell Feb-2004
US 6699745 B1 Capacitor and memory structure and method Mar-2004
US 6699747 B2 Method for increasing the capacitance in a storage trench Mar-2004
US 6700132 B2 Flat panel display device utilizing electron emission devices Mar-2004
US 6709978 B2 Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer Mar-2004
US 6709989 B2 Method for fabricating a semiconductor structure including a metal oxide interface with silicon Mar-2004
US 6710538 B1 Field emission display having reduced power requirements and method Mar-2004
US 6713329 B1 Inverter made of complementary p and n channel transistors using a single directly-deposited microcrystalline silicon film Mar-2004
US 6713846 B1 Multilayer high κ dielectric films Mar-2004
US 6720216 B2 Method for forming a programmable decoder with vertical transistors Apr-2004
US 6720221 B1 Structure and method for dual gate oxide thicknesses Apr-2004
US 6723577 B1 Method of forming an optical fiber interconnect through a semiconductor wafer Apr-2004
US 6723606 B2 Aerosol process for fabricating discontinuous floating gate microelectronic devices Apr-2004
US 6727105 B1 Method of fabricating an MRAM device including spin dependent tunneling junction memory cells Apr-2004
US 6728092 B2 Formation of thin film capacitors Apr-2004
US 6730163 B2 Aluminum-containing material and atomic layer deposition methods May-2004
US 6730164 B2 Systems and methods for forming strontium- and/or barium-containing layers May-2004
US 6730367 B2 Atomic layer deposition method with point of use generated reactive gas species May-2004
US 6730575 B2 Methods of forming perovskite-type material and capacitor dielectric having perovskite-type crystalline structure May-2004
US 6731531 B1 Carburized silicon gate insulators for integrated circuits May-2004
US 6734480 B2 Semiconductor capacitors having tantalum oxide layers May-2004
US 6734510 B2 Technique to mitigate short channel effects with vertical gate transistor with different gate materials May-2004
US 6737740 B2 High performance silicon contact for flip chip May-2004
US 6737887 B2 Current mode signal interconnects and CMOS amplifier May-2004
US 6740605 B1 Process for reducing hydrogen contamination in dielectric materials in memory devices May-2004
US 6744063 B2 Image pickup device including electron-emitting devices Jun-2004
US 6744093 B2 Multilayer electrode for a ferroelectric capacitor Jun-2004
US 6746893 B1 Transistor with variable electron affinity gate and methods of fabrication and use Jun-2004
US 6746930 B2 Oxygen barrier for cell container process Jun-2004
US 6746934 B2 Atomic layer doping apparatus and method Jun-2004
US 6750066 B1 Precision high-K intergate dielectric layer Jun-2004
US 6754108 B2 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Jun-2004
US 6755886 B2 Method for producing metallic microparticles Jun-2004
US 6756237 B2 Reduction of noise, and optimization of magnetic field sensitivity and electrical properties in magnetic tunnel junction devices Jun-2004
US 6756298 B2 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals Jun-2004
US 6759081 B2 Method of depositing thin films for magnetic heads Jul-2004
US 6762114 B1 Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness Jul-2004
US 6764901 B2 Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor Jul-2004
US 6767419 B1 Methods of forming hardened surfaces Jul-2004
US 6767582 B1 Method of modifying source chemicals in an ald process Jul-2004
US 6767795 B2 Highly reliable amorphous high-k gate dielectric ZrOXNY Jul-2004
US 6768175 B1 Semiconductor substrate and its production method, semiconductor device comprising the same and its production method Jul-2004
US 6770536 B2 Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate Aug-2004
US 6770923 B2 High K dielectric film Aug-2004
US 6773981 B1 Methods of forming capacitors Aug-2004
US 6774050 B2 Doped aluminum oxide dielectrics Aug-2004
US 6777353 B2 Process for producing oxide thin films Aug-2004
US 6777715 B1 Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same Aug-2004
US 6777739 B2 Multilayer electrode for a ferroelectric capacitor Aug-2004
US 6778441 B2 Integrated circuit memory device and method Aug-2004
US 6780704 B1 Conformal thin films over textured capacitor electrodes Aug-2004
US 6784049 B2 Method for forming refractory metal oxide layers with tetramethyldisiloxane Aug-2004
US 6787122 B2 Method of making nanotube-based material with enhanced electron field emission properties Sep-2004
US 6787370 B2 Method of forming a weak ferroelectric transistor Sep-2004
US 6787413 B2 Capacitor structure forming methods Sep-2004
US 6787463 B2 Chemical vapor deposition methods, and atomic layer deposition method Sep-2004
US 6787888 B2 High permeability composite films to reduce noise in high speed interconnects Sep-2004
US 6787906 B1 Bit line pad and borderless contact on bit line stud with localized etch stop layer formed in an undermined region Sep-2004
US 6787992 B2 Display device of flat panel structure with emission devices of matrix array Sep-2004
US 6790791 B2 Lanthanide doped TiOx dielectric films Sep-2004
US 6794255 B1 Carburized silicon gate insulators for integrated circuits Sep-2004
US 6794284 B2 Systems and methods for forming refractory metal nitride layers using disilazanes Sep-2004
US 6794315 B1 Ultrathin oxide films on semiconductors Sep-2004
US 6794709 B2 Structure and method for dual gate oxide thicknesses Sep-2004
US 6794735 B2 High permeability composite films to reduce noise in high speed interconnects Sep-2004
US 6800567 B2 Method for forming polyatomic layers Oct-2004
US 6803311 B2 Method for forming metal films Oct-2004
US 6803326 B2 Porous silicon oxycarbide integrated circuit insulator Oct-2004
US 6804136 B2 Write once read only memory employing charge trapping in insulators Oct-2004
US 6806187 B2 Electrical contact for high dielectric constant capacitors and method for fabricating the same Oct-2004
US 6806211 B2 Device and method for processing substrate Oct-2004
US 6808978 B2 Method for fabricating metal electrode with atomic layer deposition (ALD) in semiconductor device Oct-2004
US 6812100 B2 Evaporation of Y-Si-O films for medium-k dielectrics Nov-2004
US 6812110 B1 Methods of forming capacitor constructions, and methods of forming constructions comprising dielectric materials Nov-2004
US 6812137 B2 Method of forming coaxial integrated circuitry interconnect lines Nov-2004
US 6812157 B1 Apparatus for atomic layer chemical vapor deposition Nov-2004
US 6815804 B2 High permeability composite films to reduce noise in high speed interconnects Nov-2004
US 6818067 B2 Processing chamber for atomic layer deposition processes Nov-2004 118/715
US 6821862 B2 Methods of manufacturing integrated circuit devices that include a metal oxide layer disposed on another layer to protect the other layer from diffusion of impurities and integrated circuit devices manufactured using same Nov-2004
US 6821873 B2 Anneal sequence for high-κ film property optimization Nov-2004
US 6828632 B2 Stable PD-SOI devices and methods Dec-2004
US 6828656 B2 High performance silicon contact for flip chip and a system using same Dec-2004
US 6830676 B2 Coking and carburization resistant iron aluminides for hydrocarbon cracking Dec-2004
US 6831315 B2 Conformal thin films over textured capacitor electrodes Dec-2004
US 6833285 B1 Method of making a chip packaging device having an interposer Dec-2004
US 6833308 B2 Structure and method for dual gate oxide thicknesses Dec-2004
US 6833317 B2 High permeability composite films to reduce noise in high speed interconnects Dec-2004
US 6835111 B2 Field emission display having porous silicon dioxide layer Dec-2004
US 6838404 B2 Metal alkoxides and methods of making same Jan-2005
US 6842370 B2 Vertical NROM having a storage density of 1 bit per 1F2 Jan-2005
US 6844203 B2 Gate oxides, and methods of forming Jan-2005
US 6844256 B2 High permeability composite films to reduce noise in high speed interconnects Jan-2005
US 6844260 B2 Insitu post atomic layer deposition destruction of active species Jan-2005
US 6844319 B1 Peptide-based carrier devices for stellate cells Jan-2005
US 6846574 B2 Honeycomb structure thermal barrier coating Jan-2005
US 6846738 B2 High permeability composite films to reduce noise in high speed interconnects Jan-2005
US 6852167 B2 Methods, systems, and apparatus for uniform chemical-vapor depositions Feb-2005
US 6852613 B2 High permeability thin films and patterned thin films to reduce noise in high speed interconnections Feb-2005
US 6853587 B2 Vertical NROM having a storage density of 1 bit per 1F2 Feb-2005
US 6858120 B2 Method and apparatus for the fabrication of ferroelectric films Feb-2005
US 6858444 B2 Method for making a ferroelectric memory transistor Feb-2005
US 6858865 B2 Doped aluminum oxide dielectrics Feb-2005
US 6863725 B2 Method of forming a Ta2O5 comprising layer Mar-2005
US 6863933 B2 Method of hydrophilizing materials Mar-2005
US 6884706 B2 High permeability thin films and patterned thin films to reduce noise in high speed interconnections Apr-2005
US 6884719 B2 Method for depositing a coating having a relatively high dielectric constant onto a substrate Apr-2005
US 6884739 B2 Lanthanide doped TiOx dielectric films by plasma oxidation Apr-2005
US 6887758 B2 Non-volatile memory device and method for forming May-2005
US 6888739 B2 Nanocrystal write once read only memory for archival storage May-2005
US 6890843 B2 Methods of forming semiconductor structures May-2005
US 6893984 B2 Evaporated LaA1O3 films for gate dielectrics May-2005
US 6900116 B2 High permeability thin films and patterned thin films to reduce noise in high speed interconnections May-2005
US 6900122 B2 Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics May-2005
US 6900481 B2 Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors May-2005
US 6903003 B2 High permeability composite films to reduce noise in high speed interconnects Jun-2005
US 6903367 B2 Programmable memory address and decode circuits with vertical body transistors Jun-2005
US 6903444 B2 High permeability thin films and patterned thin films to reduce noise in high speed interconnections Jun-2005
US 6906402 B2 High permeability thin films and patterned thin films to reduce noise in high speed interconnections Jun-2005
US 6914278 B2 High permeability thin films and patterned thin films to reduce noise in high speed interconnections Jul-2005
US 6914800 B2 Structures, methods, and systems for ferroelectric memory transistors Jul-2005
US 6919266 B2 Copper technology for ULSI metallization Jul-2005
US 6921702 B2 Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics Jul-2005
US 6929830 B2 Plasma treatment method and method of manufacturing optical parts using the same Aug-2005
US 6930346 B2 Evaporation of Y-Si-O films for medium-K dielectrics Aug-2005
US 6933225 B2 Graded thin films Aug-2005
US 6952032 B2 Programmable array logic or memory devices with asymmetrical tunnel barriers Oct-2005
US 6953730 B2 Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics Oct-2005
US 6955968 B2 Graded composition gate insulators to reduce tunneling barriers in flash memory devices Oct-2005
US 6958300 B2 Systems and methods for forming metal oxides using metal organo-amines and metal organo-oxides Oct-2005
US 6958302 B2 Atomic layer deposited Zr-Sn-Ti-O films using TiI4 Oct-2005
US 6958937 B2 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Oct-2005
US 6960538 B2 Composite dielectric forming methods and composite dielectrics Nov-2005
US 6963103 B2 SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Nov-2005
US 6967159 B2 Systems and methods for forming refractory metal nitride layers using organic amines Nov-2005
US 6970053 B2 Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection Nov-2005
US 6979855 B2 High-quality praseodymium gate dielectrics Dec-2005
US 6984592 B2 Systems and methods for forming metal-doped alumina Jan-2006
US 6989573 B2 Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics Jan-2006
US 6995057 B2 Folded bit line DRAM with vertical ultra thin body transistors Feb-2006
US 6995081 B2 Systems and methods for forming tantalum silicide layers Feb-2006
US 7012297 B2 Scalable flash/NV structures and devices with extended endurance Mar-2006
US 7012311 B2 Semiconductor device formed on (111) surface of a Si crystal and fabrication process thereof Mar-2006
US 7015525 B2 Folded bit line DRAM with vertical ultra thin body transistors Mar-2006
US 7026694 B2 Lanthanide doped TiOx dielectric films by plasma oxidation Apr-2006
US 7030042 B2 Systems and methods for forming tantalum oxide layers and tantalum precursor compounds Apr-2006
US 7037574 B2 Atomic layer deposition for fabricating thin films May-2006 428/200
US 7041609 B2 Systems and methods for forming metal oxides using alcohols May-2006
US 7042043 B2 Programmable array logic or memory devices with asymmetrical tunnel barriers May-2006
US 7045430 B2 Atomic layer-deposited LaAlO3 films for gate dielectrics May-2006
US 7049192 B2 Lanthanide oxide / hafnium oxide dielectrics May-2006
US 7064058 B2 Low-temperature growth high-quality ultra-thin praseodymium gate dieletrics Jun-2006
US 7068544 B2 Flash memory with low tunnel barrier interpoly insulators Jun-2006
US 7074673 B2 Service programmable logic arrays with low tunnel barrier interpoly insulators Jul-2006
US 7075829 B2 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Jul-2006
US 7077902 B2 Atomic layer deposition methods Jul-2006
US 7081421 B2 Lanthanide oxide dielectric layer Jul-2006
US 7084078 B2 Atomic layer deposited lanthanide doped TiOx dielectric films Aug-2006
US 7087481 B2 Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands Aug-2006
US 7087954 B2 In service programmable logic arrays with low tunnel barrier interpoly insulators Aug-2006
US 7101813 B2 Atomic layer deposited Zr-Sn-Ti-O films Sep-2006
US 7112485 B2 Systems and methods for forming zirconium and/or hafnium-containing layers Sep-2006
US 7115166 B2 Systems and methods for forming strontium- and/or barium-containing layers Oct-2006
US 7115528 B2 Systems and method for forming silicon oxide layers Oct-2006
US 7115566 B2 Compounds and method for the prevention and treatment of diabetic retinopathy Oct-2006
US 7122464 B2 Systems and methods of forming refractory metal nitride layers using disilazanes Oct-2006
US 7125815 B2 Methods of forming a phosphorous doped silicon dioxide comprising layer Oct-2006
US 7129553 B2 Lanthanide oxide/hafnium oxide dielectrics Oct-2006
US 7135369 B2 Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9 Nov-2006
US 7135421 B2 Atomic layer-deposited hafnium aluminum oxide Nov-2006
US 7138336 B2 Plasma enhanced atomic layer deposition (PEALD) equipment and method of forming a conducting thin film using the same thereof Nov-2006
US 7154354 B2 High permeability layered magnetic films to reduce noise in high speed interconnection Dec-2006
US 7160577 B2 Methods for atomic-layer deposition of aluminum oxides in integrated circuits Jan-2007 427/255.31
US 7160817 B2 Dielectric material forming methods Jan-2007
US 7166886 B2 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Jan-2007
US 7169673 B2 Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics Jan-2007
US 7183186 B2 Atomic layer deposited ZrTiO4 films Feb-2007
US 7187587 B2 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Mar-2007
US 7192824 B2 Lanthanide oxide / hafnium oxide dielectric layers Mar-2007
US 7192892 B2 Atomic layer deposited dielectric layers Mar-2007
US 7195999 B2 Metal-substituted transistor gates Mar-2007
US 7196007 B2 Systems and methods of forming refractory metal nitride layers using disilazanes Mar-2007
US 7199023 B2 Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed Apr-2007
US 7205218 B2 Method including forming gate dielectrics having multiple lanthanide oxide layers Apr-2007
US 7211492 B2 Self aligned metal gates on high-k dielectrics May-2007
US 7214994 B2 Self aligned metal gates on high-k dielectrics May-2007
US 7221017 B2 Memory utilizing oxide-conductor nanolaminates May-2007
US 7221586 B2 Memory utilizing oxide nanolaminates May-2007
US 7235501 B2 Lanthanum hafnium oxide dielectrics Jun-2007
US 7235854 B2 Lanthanide doped TiOx dielectric films Jun-2007
US 7250367 B2 Deposition methods using heteroleptic precursors Jul-2007
US 7253122 B2 Systems and methods for forming metal oxides using metal diketonates and/or ketoimines Aug-2007
US 7271077 B2 Deposition methods with time spaced and time abutting precursor pulses Sep-2007
US 7274067 B2 Service programmable logic arrays with low tunnel barrier interpoly insulators Sep-2007
US 7294556 B2 Method of forming trench isolation in the fabrication of integrated circuitry Nov-2007
US 7300870 B2 Systems and methods of forming refractory metal nitride layers using organic amines Nov-2007
US 7309664 B1 Substrate with a photocatalytic coating Dec-2007
US 7312494 B2 Lanthanide oxide / hafnium oxide dielectric layers Dec-2007
US 7326980 B2 Devices with HfSiON dielectric films which are Hf-O rich Feb-2008
US 7332442 B2 Systems and methods for forming metal oxide layers Feb-2008
US 7374617 B2 Atomic layer deposition methods and chemical vapor deposition methods Mar-2008
US 7365027 B2 ALD of amorphous lanthanide doped TiOx films Apr-2008
US 7368402 B2 Systems and methods for forming tantalum oxide layers and tantalum precursor compounds May-2008
US 7374964 B2 Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics May-2008
US 7388246 B2 Lanthanide doped TiOx dielectric films Jun-2008
US 7390756 B2 Atomic layer deposited zirconium silicon oxide films Jun-2008
US 7402876 B2 Zr— Sn—Ti—O films Jul-2008
US 7405454 B2 Electronic apparatus with deposited dielectric layers Jul-2008
US 7410668 B2 Methods, systems, and apparatus for uniform chemical-vapor depositions Aug-2008
US 7410910 B2 Lanthanum aluminum oxynitride dielectric films Aug-2008
US 7410917 B2 Atomic layer deposited Zr-Sn-Ti-O films using TiI4 Aug-2008
US 7410918 B2 Systems and methods for forming metal oxides using alcohols Aug-2008
US 7411237 B2 Lanthanum hafnium oxide dielectrics Aug-2008
US 7439194 B2 Lanthanide doped TiOx dielectric films by plasma oxidation Oct-2008
US 7508025 B2 Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators Mar-2009
US 7508648 B2 Atomic layer deposition of Dy doped HfO2 films as gate dielectrics Mar-2009
US 7510983 B2 Iridium/zirconium oxide structure Mar-2009
US 7518246 B2 Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics Apr-2009
US 7531869 B2 Lanthanum aluminum oxynitride dielectric films May-2009
US 2001/0002280 A1 Radical-assisted sequential CVD May-2001
US 2001/0002582 A1 Method and apparatus for providing uniform gas delivery to substrates in CVD and PECVD processes Jun-2001
US 2001/0009383 A1 Semiconductor integrated circuit and its fabrication method Jul-2001
US 2001/0009695 A1 Process for growing metalloid thin films Jul-2001
US 2001/0010957 A1 Memory cell with vertical transistor and buried word and body lines Aug-2001
US 2001/0012698 A1 Metal oxide thin films for high dielectric constant application Aug-2001
US 2001/0024387 A1 Conformal thin films over textured capacitor electrodes Sep-2001
US 2001/0030352 A1 Method for increasing the capacitance in a storage trench and trench capacitor having increased capacitance Oct-2001
US 2001/0042505 A1 Precursor mixtures for use in preparing layers on substrates Nov-2001
US 2001/0051406 A1 Fabrication of dram and other semiconductor devices with an insulating film using a wet rapid thermal oxidation process Dec-2001
US 2001/0051442 A1 Method for producing high surface area foil electrodes Dec-2001
US 2001/0053096 A1 Dynamic flash memory cells with ultra thin tunnel oxides Dec-2001
US 2001/0053577 A1 Method of fabricating a semiconductor-on-insulator memory cell with buried word and body lines Dec-2001
US 2002/0000593 A1 Semiconductor device and method of manufacturing the same Jan-2002
US 2002/0001219 A1 Discrete devices including eaprom transistor and nvram memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatus including same Jan-2002
US 2002/0001971 A1 Methods of manufacturing integrated circuit devices that include a metal oxide layer disposed on another layer to protect the other layer from diffusion of impurities and integrated circuit devices manufactured using same Jan-2002
US 2002/0004276 A1 Structure and method for dual gate oxide thicknesses Jan-2002
US 2002/0004277 A1 Structure and method for dual gate oxide thicknesses Jan-2002
US 2002/0004279 A1 Capacitor forming methods and capacitor constructions Jan-2002
US 2002/0013052 A1 Methods for preparing ruthenium metal films Jan-2002
US 2002/0019116 A1 Chemical vapor deposition using organometallic precursors Feb-2002
US 2002/0019125 A1 Methods of forming materials between conductive electrical components, and insulating materials Feb-2002
US 2002/0020429 A1 Systems and methods for remote plasma clean Feb-2002
US 2002/0022156 A1 Transparent conductive oxides for plastic flat panel displays Feb-2002
US 2002/0024080 A1 Capacitor fabrication methods and capacitor constructions Feb-2002
US 2002/0025628 A1 Capacitor fabrication methods and capacitor constructions Feb-2002
US 2002/0028541 A1 Dense arrays and charge storage devices, and methods for making same Mar-2002
US 2002/0037320 A1 Method and apparatus for producing colloidal nanoparticles in a dense medium plasma Mar-2002
US 2002/0037603 A1 Microelectronic device package with conductive elements and associated method of manufacture Mar-2002
US 2002/0046705 A1 Atomic layer doping apparatus and method Apr-2002
US 2002/0046993 A1 Electrothermal gun for direct electrothermal-physical conversion of precursor into nanopowder Apr-2002
US 2002/0051859 A1 Optical recording medium May-2002
US 2002/0053869 A1 Field emission display having reduced power requirements and method May-2002
US 2002/0058578 A1 Glass ceramic and temperature compensating member May-2002
US 2002/0068466 A1 Methods of forming thin films by atomic layer deposition Jun-2002
US 2002/0072164 A1 Processing chamber with multi-layer brazed lid Jun-2002
US 2002/0076070 A1 Speaker Jun-2002
US 2002/0083464 A1 System and method for unprompted, context-sensitive querying during a televison broadcast Jun-2002
US 2002/0084480 A1 Top electrode in a strongly oxidizing environment Jul-2002
US 2002/0086507 A1 Method of forming a metal gate in a semiconductor device Jul-2002
US 2002/0086521 A1 Methods of forming silicon-doped aluminum oxide, and methods of forming transistors and memory devices Jul-2002
US 2002/0086555 A1 Methods of forming silicon-Doped Aluminum oxide, and methods of forming tranisistors and memory devices Jul-2002
US 2002/0089023 A1 Low leakage current metal oxide-nitrides and method of fabricating same Jul-2002
US 2002/0089063 A1 Copper dual damascene interconnect technology Jul-2002
US 2002/0090806 A1 Copper dual damascene interconnect technology Jul-2002
US 2002/0094632 A1 Capacitor fabrication methods and capacitor constructions Jul-2002
US 2002/0100418 A1 Versatile atomic layer deposition apparatus Aug-2002
US 2002/0102818 A1 Deposition methods and apparatuses providing surface activation Aug-2002
US 2002/0105087 A1 High performance silicon contact for flip chip Aug-2002
US 2002/0109138 A1 Programmable memory address and decode circuits with ultra thin vertical body transistors Aug-2002
US 2002/0109163 A1 Flash memory with ultra thin vertical body transistors Aug-2002
US 2002/0110991 A1 Sequential pulse deposition Aug-2002
US 2002/0111001 A1 Formation of metal oxide gate dielectric Aug-2002
US 2002/0113261 A1 Semiconductor device Aug-2002
US 2002/0117704 A1 Memory cell capacitors having an over/under configuration Aug-2002
US 2002/0117963 A1 Flat panel display device Aug-2002
US 2002/0119297 A1 Organic photosensitive optoelectronic devices with transparent electrodes Aug-2002
US 2002/0119916 A1 Elemental nanoparticles of substantially water insoluble materials Aug-2002
US 2002/0120297 A1 Vaso-occlusive implants for interventional neuroradiology Aug-2002
US 2002/0122885 A1 Methods, systems, and apparatus for uniform chemical-vapor depositions Sep-2002 427/255.28
US 2002/0125490 A1 Flat panel display device utilizing electron emission devices Sep-2002
US 2002/0130338 A1 Structures, methods, and systems for ferroelectric memory transistors Sep-2002
US 2002/0130378 A1 Technique to mitigate short channel effects with vertical gate transistor with different gate materials Sep-2002
US 2002/0132374 A1 Method for controlling deposition of dielectric films Sep-2002 438/3
US 2002/0135048 A1 Doped aluminum oxide dielectrics Sep-2002
US 2002/0137271 A1 Flash memory with ultra thin vertical body transistors Sep-2002
US 2002/0142536 A1 Method of making single c-axis PGO thin film on ZrO2 for non-volatile memory applications Oct-2002
US 2002/0142569 A1 Method for fabricating a nitride read-only -memory (Nrom) Oct-2002
US 2002/0145845 A1 Formation of thin film capacitors Oct-2002
US 2002/0145901 A1 Novel transmission lines for CMOS integrated circuits Oct-2002
US 2002/0146916 A1 Semiconductor device having a high-dielectric gate insulation film and fabrication process thereof Oct-2002
US 2002/0148566 A1 Substrate processing unit Oct-2002
US 2002/0155688 A1 Highly reliable gate oxide and method of fabrication Oct-2002
US 2002/0155689 A1 Highly reliable gate oxide and method of fabrication Oct-2002
US 2002/0164420 A1 Deposition methods and apparatus for improved delivery of metastable species Nov-2002
US 2002/0167057 A1 Integrated decoupling capacitors Nov-2002
US 2002/0167089 A1 Copper dual damascene interconnect technology Nov-2002
US 2002/0170671 A1 Processing apparatus, transferring apparatus and transferring method Nov-2002
US 2002/0172799 A1 Honeycomb structure thermal barrier coating Nov-2002
US 2002/0175423 A1 High performance silicon contact for flip chip Nov-2002
US 2002/0176989 A1 Dielectric laminate for a capacitor Nov-2002
US 2002/0177244 A1 MFOS memory transistor & method of fabricating same Nov-2002
US 2002/0177282 A1 Method of forming semiconductor device having a GAA type transistor Nov-2002
US 2002/0187091 A1 Coking and carburization resistant iron aluminides for hydrocarbon cracking Dec-2002
US 2002/0190251 A1 Thin film materials of amorphous metal oxides Dec-2002
US 2002/0192366 A1 Method of hydrophilizing materials Dec-2002
US 2002/0192974 A1 Dielectric layer forming method and devices formed therewith Dec-2002
US 2002/0192975 A1 Dielectric layer forming method and devices formed therewith Dec-2002
US 2002/0192979 A1 Dielectric layer forming method and devices formed therewith Dec-2002
US 2002/0193040 A1 Method of making nanotube-based material with enhanced electron field emission properties Dec-2002
US 2002/0195056 A1 Versatile atomic layer deposition apparatus Dec-2002
US 2002/0196405 A1 LCD cell construction by mechanical thinning of a color filter substrate Dec-2002
US 2002/0197881 A1 Method for fabricating a semiconductor structure including a metal oxide interface with silicon Dec-2002
US 2003/0001190 A1 Methods for forming conductive structures and structures regarding same Jan-2003
US 2003/0001212 A1 Conductor layer nitridation Jan-2003
US 2003/0001241 A1 Semiconductor device and method of fabrication Jan-2003
US 2003/0003635 A1 Atomic layer deposition for fabricating thin films Jan-2003
US 2003/0003702 A1 Formation of metal oxide gate dielectric Jan-2003
US 2003/0003722 A1 Chemical vapor deposition systems including metal complexes with chelating O- and/or N-donor ligands Jan-2003
US 2003/0003730 A1 Sequential pulse deposition Jan-2003
US 2003/0004051 A1 Dielectric ceramic composition and method for manufacturing multilayered components using the same Jan-2003
US 2003/0008243 A1 Copper electroless deposition technology for ULSI metalization Jan-2003
US 2003/0008461 A1 Flash memory with ultra thin vertical body transistors Jan-2003
US 2003/0017717 A1 Methods for forming dielectric materials and methods for forming semiconductor devices Jan-2003
US 2003/0020169 A1 Copper technology for ULSI metallization Jan-2003
US 2003/0020180 A1 Copper technology for ULSI metallization Jan-2003
US 2003/0020429 A1 Motor controller Jan-2003
US 2003/0026697 A1 Cooling structure and method of manufacturing the same Feb-2003
US 2003/0027360 A1 Single transistor ferroelectric transistor structure with high-K insulator and method of fabricating same Feb-2003
US 2003/0030074 A1 TFT mask ROM and method for making same Feb-2003
US 2003/0032270 A1 Fabrication method for a device for regulating flow of electric current with high dielectric constant gate insulating layer and source/drain forming schottky contact or schottky-like region with substrate Feb-2003
US 2003/0040196 A1 Method of forming insulation layer in semiconductor devices for controlling the composition and the doping concentration Feb-2003
US 2003/0042512 A1 Vertical transistor and method of making Mar-2003
US 2003/0042526 A1 Method of improved high K dielectric-polysilicon interface for CMOS devices Mar-2003
US 2003/0043637 A1 Flash memory with low tunnel barrier interpoly insulators Mar-2003
US 2003/0045060 A1 Crystalline or amorphous medium-k gate oxides, Y2O3 and Gd2O3 Mar-2003
US 2003/0045078 A1 Highly reliable amorphous high-K gate oxide ZrO2 Mar-2003
US 2003/0045082 A1 Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators Mar-2003
US 2003/0048666 A1 Graded composition metal oxide tunnel barrier interpoly insulators Mar-2003
US 2003/0048745 A1 Image pickup device including electron-emitting devices Mar-2003
US 2003/0049900 A1 Graded composition gate insulators to reduce tunneling barriers in flash memory devices Mar-2003
US 2003/0049942 A1 Low temperature gate stack Mar-2003
US 2003/0052356 A1 Platinum-rhodium stack as an oxygen barrier in an integrated circuit capacitor Mar-2003
US 2003/0052358 A1 Method of improved high K dielectric - polysilicon interface for CMOS devices Mar-2003
US 2003/0059535 A1 Cycling deposition of low temperature films in a cold wall single wafer process chamber Mar-2003
US 2003/0064607 A1 Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics Apr-2003
US 2003/0089314 A1 Plasma CVD film-forming device May-2003
US 2003/0102501 A1 Rhodium-rich integrated circuit capacitor electrode Jun-2003
US 2003/0104666 A1 Method for forming dielectric stack without interfacial layer Jun-2003
US 2003/0106490 A1 Apparatus and method for fast-cycle atomic layer deposition Jun-2003 117/89
US 2003/0107402 A1 Programmable logic arrays with ultra thin body transistors Jun-2003
US 2003/0119246 A1 Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics Jun-2003
US 2003/0119291 A1 Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics Jun-2003
US 2003/0119313 A1 Processes to form a metallic film stack Jun-2003
US 2003/0130127 A1 Ultrathin dielectric oxide films Jul-2003
US 2003/0132491 A1 Highly reliable amorphous high-K gate dielectric ZrOxNy Jul-2003
US 2003/0139039 A1 Doped aluminum oxide dielectrics Jul-2003
US 2003/0141560 A1 Incorporating TCS-SiN barrier layer in dual gate CMOS devices Jul-2003
US 2003/0142569 A1 Capacitive techniques to reduce noise in high speed interconnections Jul-2003
US 2003/0143801 A1 Method of reducing oxygen vacancies and DRAM processing method Jul-2003
US 2003/0148577 A1 Controlled alignment of catalytically grown nanostructures in a large-scale synthesis process Aug-2003
US 2003/0152700 A1 Process for synthesizing uniform nanocrystalline films Aug-2003
US 2003/0157764 A1 Evaporated LaA1O3 films for gate dielectrics Aug-2003
US 2003/0159653 A1 Manifold assembly for feeding reactive precursors to substrate processing chambers Aug-2003
US 2003/0170389 A1 Atomic layer deposition with point of use generated reactive gas species Sep-2003
US 2003/0170403 A1 Atomic layer deposition apparatus and method Sep-2003
US 2003/0172872 A1 Apparatus for cyclical deposition of thin films Sep-2003
US 2003/0173652 A1 High permeability thin films and patterned thin films to reduce noise in high speed interconnections Sep-2003
US 2003/0173653 A1 High permeability thin films and patterned thin films to reduce noise in high speed interconnections Sep-2003
US 2003/0174529 A1 High permeability layered films to reduce noise in high speed interconnects Sep-2003
US 2003/0175411 A1 Precursor compositions and methods for the deposition of passive electrical components on a substrate Sep-2003
US 2003/0176023 A1 High permeability composite films to reduce noise in high speed interconnects Sep-2003
US 2003/0176025 A1 High permeability composite films to reduce noise in high speed interconnects Sep-2003
US 2003/0176049 A1 Gate dielectric and method therefor Sep-2003
US 2003/0176050 A1 High permeability thin films and patterned thin films to reduce noise in high speed interconnections Sep-2003
US 2003/0176052 A1 High permeability thin films and patterned thin films to reduce noise in high speed interconnections Sep-2003
US 2003/0176053 A1 High permeability thin films and patterned thin films to reduce noise in high speed interconnections Sep-2003
US 2003/0176065 A1 Aluminum-containing material and atomic layer deposition methods Sep-2003
US 2003/0181039 A1 Semiconductor device with novel film composition Sep-2003
US 2003/0183156 A1 Chemical vapor deposition methods, atomic layer deposition methods, and valve assemblies for use with a reactive precursor in semiconductor processing Oct-2003
US 2003/0194861 A1 Reactive gaseous deposition precursor feed apparatus Oct-2003
US 2003/0194862 A1 Chemical vapor deposition methods, and atomic layer deposition method Oct-2003
US 2003/0196513 A1 Method for producing metallic microparticles Oct-2003
US 2003/0200917 A1 Atomic layer deposition methods and chemical vapor deposition methods Oct-2003
US 2003/0203626 A1 Apparatus and method for forming thin layers of materials on micro-device workpieces Oct-2003
US 2003/0207032 A1 Methods, systems, and apparatus for atomic-layer deposition of aluminum oxides in integrated circuits Nov-2003
US 2003/0207540 A1 Atomic layer-deposited laaio3 films for gate dielectrics Nov-2003
US 2003/0207564 A1 Copper dual damascene interconnect technology Nov-2003
US 2003/0207566 A1 High performance silicon contact for flip chip Nov-2003
US 2003/0207593 A1 Atomic layer deposition and conversion Nov-2003
US 2003/0209324 A1 Plasma reactor with reduced reaction chamber Nov-2003
US 2003/0213987 A1 MIS capacitor and method of formation Nov-2003
US 2003/0218199 A1 Open bit line DRAM with ultra-thin body transistors Nov-2003
US 2003/0222300 A1 Capacitor constructions, semiconductor constructions, and methods of forming electrical contacts and semiconductor constructions Dec-2003
US 2003/0224600 A1 Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor Dec-2003
US 2003/0227033 A1 Atomic layer-deposited HfA1O3 films for gate dielectrics Dec-2003
US 2003/0228747 A1 Pr2O3-based la-oxide gate dielectrics Dec-2003
US 2003/0232511 A1 ALD metal oxide deposition process using direct oxidation Dec-2003
US 2003/0234420 A1 Write once read only memory with large work function floating gates Dec-2003
US 2003/0235066 A1 Ferroelectric write once read only memory for archival storage Dec-2003
US 2003/0235076 A1 Multistate NROM having a storage density much greater than 1 Bit per 1F2 Dec-2003
US 2003/0235961 A1 Cyclical sequential deposition of multicomponent films Dec-2003
US 2004/0004244 A1 Structures, methods, and systems for ferroelectric memory transistors Jan-2004
US 2004/0004245 A1 Memory utilizing oxide-conductor nanolaminates Jan-2004
US 2004/0004247 A1 Memory utilizing oxide-nitride nanolaminates Jan-2004
US 2004/0004859 A1 Memory utilizing oxide nanolaminates Jan-2004
US 2004/0007171 A1 Method for growing thin oxide films Jan-2004
US 2004/0009679 A1 Method of forming material using atomic layer deposition and method of forming capacitor of semiconductor device using the same Jan-2004
US 2004/0016944 A1 Integrated decoupling capacitors Jan-2004
US 2004/0023461 A1 Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics Feb-2004
US 2004/0028811 A1 Bismuth titanium silicon oxide, bismuth titanium silicon oxide thin film, and method for forming the thin film Feb-2004
US 2004/0032773 A1 Programmable memory address and decode circuits with vertical body transistors Feb-2004
US 2004/0033661 A1 Semiconductor device and method for manufacturing the same Feb-2004
US 2004/0033681 A1 Lanthanide doped TiOx dielectric films by plasma oxidation Feb-2004
US 2004/0033701 A1 Lanthanide doped tiox dielectric films Feb-2004
US 2004/0036129 A1 Atomic layer deposition of CMOS gates with variable work functions Feb-2004
US 2004/0038525 A1 Enhanced atomic layer deposition Feb-2004
US 2004/0038554 A1 Composite dielectric forming methods and composite dielectrics Feb-2004
US 2004/0040501 A1 Systems and methods for forming zirconium and/or hafnium-containing layers Mar-2004
US 2004/0042256 A1 Single transistor vertical memory gain cell Mar-2004
US 2004/0043151 A1 Systems and methods for forming tantalum silicide layers Mar-2004
US 2004/0043541 A1 Atomic layer deposited lanthanide doped TiOx dielectric films Mar-2004
US 2004/0043557 A1 Methods for making a dielectric stack in an integrated circuit Mar-2004
US 2004/0043569 A1 Atomic layer deposited HfSiON dielectric films Mar-2004
US 2004/0043600 A1 Systems and methods for forming refractory metal nitride layers using organic amines Mar-2004
US 2004/0043604 A1 Systems and methods for forming refractory metal nitride layers using disilazanes Mar-2004
US 2004/0043625 A1 Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands Mar-2004
US 2004/0043630 A1 Systems and methods for forming metal oxides using metal organo-amines and metal organo-oxides Mar-2004
US 2004/0043632 A1 Systems and methods for forming metal oxides using alcohols Mar-2004
US 2004/0043633 A1 Systems and methods for forming refractory metal oxide layers Mar-2004
US 2004/0043634 A1 Systems and methods for forming metal-doped alumina Mar-2004
US 2004/0043635 A1 Systems and methods for forming metal oxides using metal diketonates and/or ketoimines Mar-2004
US 2004/0043636 A1 Systems and methods for forming tantalum oxide layers and tantalum precursor compounds Mar-2004
US 2004/0065255 A1 Cyclical layer deposition system Apr-2004
US 2004/0086897 A1 Nanoparticle probes with Raman Spectroscopic fingerprints for analyte detection May-2004
US 2004/0087124 A1 Method for fabricating semiconductor device May-2004
US 2004/0099889 A1 Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrate May-2004
US 2004/0110348 A1 Atomic layer deposited Zr-Sn-Ti-O films using TiI4 Jun-2004
US 2004/0110391 A1 Atomic layer deposited Zr-Sn-Ti-O films Jun-2004
US 2004/0126954 A1 Deposition methods with time spaced and time abutting precursor pulses Jul-2004
US 2004/0130951 A1 Write once read only memory employing charge trapping in insulators Jul-2004
US 2004/0140513 A1 Atomic layer deposition of CMOS gates with variable work functions Jul-2004
US 2004/0144980 A1 Atomic layer deposition of metal oxynitride layers as gate dielectrics and semiconductor device structures utilizing metal oxynitride layers Jul-2004
US 2004/0152254 A1 Method of forming a Ta2O5 comprising layer Aug-2004
US 2004/0164357 A1 Atomic layer-deposited LaAIO3 films for gate dielectrics Aug-2004
US 2004/0164365 A1 Lanthanide doped TiOx dielectric films Aug-2004
US 2004/0165412 A1 Ferroelectric write once read only memory for archival storage Aug-2004
US 2004/0168627 A1 Atomic layer deposition of oxide film Sep-2004
US 2004/0169453 A1 Field emission display having reduced power requirements and method Sep-2004
US 2004/0171280 A1 Atomic layer deposition of nanolaminate film Sep-2004
US 2004/0175882 A1 Atomic layer deposited dielectric layers Sep-2004
US 2004/0178439 A1 Doped aluminum oxide dielectrics Sep-2004
US 2004/0183108 A1 Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics Sep-2004
US 2004/0185630 A1 Technique to mitigate short channel effects with vertical gate transistor with different gate materials Sep-2004
US 2004/0185654 A1 Low-temperature growth high-quality ultra-thin praseodymium gate dielectrics Sep-2004
US 2004/0187968 A1 Atomic layer deposition methods Sep-2004
US 2004/0189175 A1 Field emission display having reduced power requirements and method Sep-2004
US 2004/0197946 A1 Systems and methods for forming strontium-and/or barium-containing layers Oct-2004
US 2004/0202032 A1 Vertical NROM having a storage density of 1 bit per 1F2 Oct-2004
US 2004/0203254 A1 Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films Oct-2004
US 2004/0214399 A1 Atomic layer deposited ZrTiO4 films Oct-2004
US 2004/0219746 A1 Systems and methods for forming metal oxide layers Nov-2004
US 2004/0219783 A1 Copper dual damascene interconnect technology Nov-2004
US 2004/0222476 A1 Highly reliable amorphous high-k gate dielectric ZrOxNy Nov-2004
US 2004/0224505 A1 Nanolayer thick film processing system and method Nov-2004
US 2004/0235313 A1 Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrate Nov-2004
US 2004/0248398 A1 Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow Dec-2004
US 2004/0262700 A1 Lanthanide oxide / hafnium oxide dielectrics Dec-2004
US 2004/0266217 A1 Method of forming high dielectric film using atomic layer deposition and method of manufacturing capacitor having the high dielectric film Dec-2004
US 2005/0006727 A1 High permeability composite films to reduce noise in high speed interconnects Jan-2005
US 2005/0007817 A1 High permeability composite films to reduce noise in high speed interconnects Jan-2005
US 2005/0009266 A1 Systems and methods for forming refractory metal oxide layers Jan-2005
US 2005/0009335 A1 Apparatuses for treating pluralities of discrete semiconductor substrates; and methods for treating pluralities of discrete semiconductor substrates Jan-2005
US 2005/0009368 A1 Methods of forming a phosphorus doped silicon dioxide comprising layer, and methods of forming trench isolation in the fabrication of integrated circuitry Jan-2005
US 2005/0009370 A1 Composite dielectric forming methods and composite dielectrics Jan-2005
US 2005/0017327 A1 High permeability composite films to reduce noise in high speed interconnects Jan-2005
US 2005/0019978 A1 Systems and methods for forming tantalum oxide layers and tantalum precursor compounds Jan-2005
US 2005/0020017 A1 Lanthanide oxide / hafnium oxide dielectric layers Jan-2005
US 2005/0023574 A1 Memory utilizing oxide-nitride nanolaminates Feb-2005
US 2005/0023578 A1 Stable PD-SOI devices and methods Feb-2005
US 2005/0023584 A1 Atomic layer deposition and conversion Feb-2005
US 2005/0023594 A1 Pr2O3-based la-oxide gate dielectrics Feb-2005
US 2005/0023595 A1 Programmable array logic or memory devices with asymmetrical tunnel barriers Feb-2005
US 2005/0023602 A1 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Feb-2005
US 2005/0023613 A1 Stable PD-SOI devices and methods Feb-2005
US 2005/0023624 A1 Atomic layer-deposited HfAlO3 films for gate dielectrics Feb-2005
US 2005/0023625 A1 Atomic layer deposited HfSiON dielectric films Feb-2005
US 2005/0023626 A1 Lanthanide oxide / hafnium oxide dielectrics Feb-2005
US 2005/0023627 A1 Lanthanide doped TiOx dielectric films by plasma oxidation Feb-2005
US 2005/0023650 A1 Capacitive techniques to reduce noise in high speed interconnections Feb-2005
US 2005/0024092 A1 Pseudo CMOS dynamic logic with delayed clocks Feb-2005
US 2005/0026349 A1 Flash memory with low tunnel barrier interpoly insulators Feb-2005
US 2005/0026374 A1 Evaporation of Y-Si-O films for medium-K dielectrics Feb-2005
US 2005/0026375 A1 Write once read only memory employing charge trapping in insulators Feb-2005
US 2005/0026458 A1 Methods of forming hafnium-containing materials, methods of forming hafnium oxide, and constructions comprising hafnium oxide Feb-2005
US 2005/0028733 A1 Systems and methods of forming refractory metal nitride layers using disilazanes Feb-2005
US 2005/0029545 A1 Method for forming programmable logic arrays using vertical gate transistors Feb-2005
US 2005/0029547 A1 Lanthanide oxide / hafnium oxide dielectric layers Feb-2005
US 2005/0029604 A1 Atomic layer deposited Zr-Sn-Ti-O films using TiI4 Feb-2005
US 2005/0029605 A1 Highly reliable amorphous high-k gate oxide ZrO2 Feb-2005
US 2005/0030803 A1 High permeability layered films to reduce noise in high speed interconnects Feb-2005
US 2005/0030825 A1 Structures, methods, and systems for ferroelectric memory transistors Feb-2005
US 2005/0032292 A1 Crystalline or amorphous medium-K gate oxides, Y2O3 and Gd2O3 Feb-2005
US 2005/0032342 A1 Atomic layer deposition of CMOS gates with variable work functions Feb-2005
US 2005/0032360 A1 Systems and methods of forming refractory metal nitride layers using disilazanes Feb-2005
US 2005/0034662 A1 Methods, systems, and apparatus for uniform chemical-vapor depositions Feb-2005
US 2005/0036370 A1 Write once read only memory with large work function floating gates Feb-2005
US 2005/0037563 A1 Capacitor structures Feb-2005
US 2005/0040034 A1 Coating method and coating Feb-2005
US 2005/0054165 A1 Atomic layer deposited ZrAlxOy dielectric layers Mar-2005
US 2005/0077519 A1 Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics Apr-2005
US 2005/0087134 A1 Methods, systems, and apparatus for uniform chemical-vapor depositions Apr-2005
US 2005/0124171 A1 Method of forming trench isolation in the fabrication of integrated circuitry Jun-2005
US 2005/0124174 A1 Lanthanide doped TiOx dielectric films by plasma oxidation Jun-2005
US 2005/0124175 A1 Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics Jun-2005
US 2005/0136689 A9 Systems and methods for forming metal oxides using alcohols Jun-2005
US 2005/0138262 A1 Flash memory having a high-permittivity tunnel dielectric Jun-2005
US 2005/0145911 A1 Memory having a vertical transistor Jul-2005
US 2005/0145957 A1 Evaporated LaAlO3 films for gate dielectrics Jul-2005
US 2005/0145959 A1 Technique to mitigate short channel effects with vertical gate transistor with different gate materials Jul-2005
US 2005/0158973 A1 Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics Jul-2005
US 2005/0160981 A9 Systems and methods for forming zirconium and/or hafnium-containing layers Jul-2005
US 2005/0164521 A1 Zr-Sn-Ti-O films Jul-2005
US 2005/0169054 A1 SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Aug-2005
US 2005/0190617 A1 Folded bit line DRAM with vertical ultra thin body transistors Sep-2005
US 2005/0221006 A1 Metal-doped alumina and layers thereof Oct-2005
US 2005/0227442 A1 Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics Oct-2005
US 2005/0260357 A1 Stabilization of high-k dielectric materials Nov-2005
US 2005/0277256 A1 Nanolaminates of hafnium oxide and zirconium oxide Dec-2005
US 2005/0280067 A1 Atomic layer deposited zirconium titanium oxide films Dec-2005
US 2005/0285225 A1 Semiconductor constructions comprising cerium oxide and titanium oxide Dec-2005
US 2005/0287804 A1 Systems and methods of forming refractory metal nitride layers using organic amines Dec-2005
US 2005/0287819 A1 Systems and methods for forming metal oxides using metal organo-amines and metal organo-oxides Dec-2005
US 2006/0000412 A1 Systems and apparatus for atomic-layer deposition Jan-2006
US 2006/0001151 A1 Atomic layer deposited dielectric layers Jan-2006
US 2006/0003517 A1 Atomic layer deposited Zr-Sn-Ti-O films using TiI4 Jan-2006
US 2006/0008966 A1 Memory utilizing oxide-conductor nanolaminates Jan-2006
US 2006/0023513 A1 High density stepped, non-planar nitride read only memory Feb-2006
US 2006/0024975 A1 Atomic layer deposition of zirconium-doped tantalum oxide films Feb-2006
US 2006/0028867 A1 Non-planar flash memory having shielding between floating gates Feb-2006
US 2006/0028869 A1 High density stepped, non-planar flash memory Feb-2006
US 2006/0043492 A1 Ruthenium gate for a lanthanide oxide dielectric layer Mar-2006
US 2006/0043504 A1 Atomic layer deposited titanium aluminum oxide films Mar-2006
US 2006/0046505 A1 Ruthenium gate for a lanthanide oxide dielectric layer Mar-2006
US 2006/0046521 A1 Deposition methods using heteroleptic precursors Mar-2006
US 2006/0046522 A1 Atomic layer deposited lanthanum aluminum oxide dielectric layer Mar-2006
US 2006/0048711 A1 Systems and methods of forming tantalum silicide layers Mar-2006
US 2006/0125030 A1 Hybrid ALD-CVD of PrxOy/ZrO2 films as gate dielectrics Jun-2006
US 2006/0128168 A1 Atomic layer deposited lanthanum hafnium oxide dielectrics Jun-2006
US 2006/0148180 A1 Atomic layer deposited hafnium tantalum oxide dielectrics Jul-2006
US 2006/0172485 A1 Systems and methods for forming metal oxides using alcohols Aug-2006
US 2006/0176645 A1 Atomic layer deposition of Dy doped HfO2 films as gate dielectrics Aug-2006
US 2006/0177975 A1 Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics Aug-2006
US 2006/0183272 A1 Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics Aug-2006
US 2006/0189154 A1 Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics Aug-2006
US 2006/0223337 A1 Atomic layer deposited titanium silicon oxide films Oct-2006
US 2006/0228868 A1 ALD of amorphous lanthanide doped TiOx films Oct-2006
US 2006/0231017 A1 Atomic layer deposition methods and chemical vapor deposition methods Oct-2006
US 2006/0231889 A1 Two-terminal solid-state memory device and two-terminal flexible memory device based on nanocrystals or nanoparticles Oct-2006
US 2006/0237764 A1 Lanthanide doped tiox dielectric films Oct-2006
US 2006/0244082 A1 Atomic layer desposition of a ruthenium layer to a lanthanide oxide dielectric layer Nov-2006
US 2006/0244100 A1 Atomic layer deposited zirconium silicon oxide films Nov-2006
US 2006/0246741 A1 Atomic layer deposited nanolaminates of hfo2/Zro2 films as gate dielectrics Nov-2006
US 2006/0252211 A1 Atomic layer deposited nanolaminates of hfo2/Zro2 films as gate dielectrics Nov-2006
US 2006/0252244 A1 Systems and methods for forming metal oxide layers Nov-2006
US 2006/0252279 A1 Systems and methods for forming metal oxides using metal diketonates and/or ketoimines Nov-2006
US 2006/0255470 A1 Zralxoy dielectric layers Nov-2006
US 2006/0258097 A1 Memory utilizing oxide-nitride nanolaminates Nov-2006
US 2006/0258175 A1 Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands Nov-2006
US 2006/0261376 A1 Memory utilizing oxide-nitride nanolaminates Nov-2006
US 2006/0261389 A1 Systems and methods for forming zirconium and/or hafnium-containing layers Nov-2006
US 2006/0261397 A1 Lanthanide oxide/hafnium oxide dielectric layers Nov-2006
US 2006/0263972 A1 Atomic layer deposition of zr3n4/Zro2 films as gate dielectrics Nov-2006
US 2006/0263981 A1 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Nov-2006
US 2006/0264064 A1 Zirconium-doped tantalum oxide films Nov-2006
US 2006/0270147 A1 Hafnium titanium oxide films Nov-2006
US 2006/0274580 A1 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Dec-2006
US 2006/0281330 A1 Iridium / zirconium oxide structure Dec-2006
US 2006/0284246 A1 Memory utilizing oxide nanolaminates Dec-2006
US 2006/0292788 A1 Systems and methods of forming refractory metal nitride layers using disilazanes Dec-2006
US 2007/0006798 A1 Systems and methods for forming strontium-and/or barium-containing layers Jan-2007
US 2007/0007560 A1 Metal-substituted transistor gates Jan-2007
US 2007/0007635 A1 Self aligned metal gates on high-k dielectrics Jan-2007
US 2007/0010060 A1 Metal-substituted transistor gates Jan-2007
US 2007/0010061 A1 Metal-substituted transistor gates Jan-2007
US 2007/0018214 A1 Magnesium titanium oxide films Jan-2007
US 2007/0020835 A1 Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics Jan-2007
US 2007/0037415 A1 Lanthanum hafnium oxide dielectrics Feb-2007
US 2007/0045676 A1 Self aligned metal gates on high-k dielectrics Mar-2007
US 2007/0045752 A1 Self aligned metal gates on high-K dielectrics Mar-2007
US 2007/0048926 A1 Lanthanum aluminum oxynitride dielectric films Mar-2007
US 2007/0048989 A1 Atomic layer deposition of GdScO3 films as gate dielectrics Mar-2007
US 2007/0049023 A1 Zirconium-doped gadolinium oxide films Mar-2007
US 2007/0049051 A1 Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics Mar-2007
US 2007/0049054 A1 Cobalt titanium oxide dielectric films Mar-2007
US 2007/0059881 A1 Atomic layer deposited zirconium aluminum oxide Mar-2007
US 2007/0087563 A1 Zirconium-doped tantalum oxide films Apr-2007
US 2007/0090439 A1 Hafnium titanium oxide films Apr-2007
US 2007/0090440 A1 Lanthanum aluminum oxynitride dielectric films Apr-2007
US 2007/0090441 A1 Titanium aluminum oxide films Apr-2007
US 2007/0092989 A1 Conductive nanoparticles Apr-2007
US 2007/0099366 A1 Lanthanum aluminum oxide dielectric layer May-2007
US 2007/0105313 A1 In service programmable logic arrays with low tunnel barrier interpoly insulators May-2007
US 2007/0107661 A1 Methods, systems, and apparatus for uniform chemical-vapor depositions May-2007
US 2007/0111544 A1 Systems with a gate dielectric having multiple lanthanide oxide layers May-2007
US 2007/0131169 A1 Methods, systems, and apparatus for uniform chemical-vapor depositions Jun-2007
US 2007/0134931 A1 Lanthanide yttrium aluminum oxide dielectric films Jun-2007
US 2007/0134942 A1 Hafnium tantalum titanium oxide films Jun-2007
US 2007/0144438 A1 Systems and methods of forming refractory metal nitride layers using disilazanes Jun-2007
US 2007/0155190 A1 Systems and methods for forming metal oxide layers Jul-2007
US 2007/0158765 A1 Gallium lanthanide oxide films Jul-2007
US 2007/0161260 A1 Methods of forming a phosphorus doped silicon dioxide-comprising layer Jul-2007
US 2007/0166999 A1 Systems and methods of forming refractory metal nitride layers using disilazanes Jul-2007
US 2007/0178643 A1 Memory utilizing oxide-conductor nanolaminates Aug-2007
US 2007/0181931 A1 Hafnium tantalum oxide dielectrics Aug-2007
US 2007/0187772 A1 Ald of amorphous lanthanide doped tiox films Aug-2007
US 2007/0187831 A1 Conductive layers for hafnium silicon oxynitride films Aug-2007
US 2007/0234949 A1 Atomic layer deposited titanium-doped indium oxide films Oct-2007
US 2007/0295273 A1 Systems and methods for forming metal oxides using metal diketonates and/or ketoimines Dec-2007
US 2008/0029790 A1 ALD of silicon films on germanium Feb-2008
US 2008/0032424 A1 ALD of Zr-substituted BaTiO3 films as gate dielectrics Feb-2008
US 2008/0032465 A1 Deposition of ZrAION films Feb-2008
US 2008/0048225 A1 Atomic layer deposited barium strontium titanium oxide films Feb-2008
US 2008/0057659 A1 Hafnium aluminium oxynitride high-K dielectric and metal gates Mar-2008
US 2008/0057690 A1 Tantalum silicon oxynitride high-k dielectrics and metal gates Mar-2008
US 2008/0064210 A1 Systems and methods of forming refractory metal nitride layers using organic amines Mar-2008
US 2008/0087890 A1 Methods to form dielectric structures in semiconductor devices and resulting devices Apr-2008
US 2008/0087945 A1 Silicon lanthanide oxynitride films Apr-2008
US 2008/0102629 A1 Systems and methods of forming tantalum silicide layers May-2008
US 2008/0121962 A1 Tantalum aluminum oxynitride high-k dielectric and metal gates May-2008
US 2008/0124907 A1 Hafnium lanthanide oxynitride films May-2008
US 2008/0124908 A1 Hafnium tantalum oxynitride high-k dielectric and metal gates May-2008
US 2008/0191350 A1 Magnesium-doped zinc oxide structures and methods Aug-2008
US 2008/0191351 A1 Molybdenum-doped indium oxide structures and methods Aug-2008
US 2008/0193791 A1 Zirconium-doped zinc oxide structures and methods Aug-2008
US 2008/0194094 A1 Tungsten-doped indium oxide structures and methods Aug-2008
US 2008/0217676 A1 Zirconium silicon oxide films Sep-2008
US 2008/0248618 A1 Atomic layer deposition of ceo2/Al2o3 films as gate dielectrics Oct-2008
US 2008/0274625 A1 Methods of forming electronic devices containing zr-sn-ti-o films Nov-2008
EP 0540993 A1 Structure and fabrication of high transconductance MOS field effect transistor using a buffer layer/ferroelectric/buffer layer stack as the gate dielectric May-1993
EP 1324376 A1 Composant electronique incorporant un circuit integre et un micro-condensateur planaire Jul-2003
JP 62-199019 Search for [JP 62-199019] Sep-1987
JP 5090169 Search for [JP 5090169] Apr-1993
JP 07-320996 Search for [JP 07-320996] Dec-1995
JP 09-293845 Search for [JP 09-293845] Nov-1997
JP 11-335849 Search for [JP 11-335849] Dec-1999
JP 2000-192241 Search for [JP 2000-192241] Jul-2000
JP 2001-332546 Search for [JP 2001-332546] Nov-2001
WO WO-0233729 A2 Apr-2002
WO WO-2004079796 A3 Sep-2004
WO WO-2006026716 Mar-2006
Other References
US 6,827,790, 12/2004, Gealy et al. (withdrawn) [+370] [-370]
“Improved Metallurgy for Wiring Very Large Scale Integrated Circuits”, International Technology Disclosures, 4, Abstract,(1986),1 page.
“International Technology for Semiconductor Roadmap”, http://public.itrs.net/Files/2001ITRS/Links/1999SIARoadmap/, Semiconductor Industry Association,(1999).
Aarik, Jaan , “Atomic layer growth of epitaxial TiO2 thin films from TiCl4 and H2O on alpha -AI2O3 substrates”, Journal of Crystal Growth, 242(1-2), (2002),189-198.
Aarik, Jaan , “Influence of substrate temperature on atomic layer growth and properties of HfO2 thin films”, Thin Solid Films, 340(1-2), (1999),110-116.
Aarik, Jaan , “Phase transformations in hafnium dioxide thin films grown by atomic layer deposition at high temperatures” , Applied Surface Science, 173(1-2), (Mar. 2001),15-21.
Aarik, Jaan , “Texture development in nanocrystalline hafnium dioxide thin films grown by atomic layer deposition”, Journal of Crystal Growth, 220(1-2), (Nov. 15, 2000),105-113.
Abe, T , “Silicon Wafer-Bonding Process Technology for SOI Structures”, Extended Abstracts of the 22nd (1990 International) Conference on Solid State Devices and Materials, (1990),853-856.
Adler, E. , et al., “The Evolution of IBM CMOS DRAM Technology”, IBM Journal of Research & Development, 39(1-2), (Jan.-Mar. 1995),167-188.
Ahn, et al., “Ald of Zr-Substituted BaTiO3 Films as Gate Dielectrics”, U.S. Appl. No. 11/498,559, filed Aug. 3, 2006.
Ahn, K Y., “Atomic Layer Deposited Barium Strontium Titanium Oxide Films”, U.S. Appl. No. 11/510,803, filed Aug. 26, 2006.
Ahn, Kie Y., “Atomic Layer Deposition of GDSCO3 Films As Gate Dielectrics”, U.S. Appl. No. 11/215,507, filed Aug. 30, 2005.
Ahn, Kie Y., “Cobalt Titanium Oxide Dielectric Films”, U.S. Appl. No. 11/216,958, filed Aug. 31, 2005.
Ahn, Kie Y., “Gallium Lanthanide Oxide Films”, (U.S. Appl. No. 11/329,025, filed Jan. 10, 2006.
Ahn, Kie Y., et al., “Hafnium Lanthanide Oxynitride Films”, U.S. Appl. No. 11/515,143, filed Aug. 31, 2006.
Ahn, “Iridium / Zirconium Oxide Structure”, U.S. Appl. No. 11/152,759, filed Jun. 14, 2005.
Ahn, Kie Y., et al., “Lanthanide Yttrium Aluminum Oxide Dielectric Films”, U.S. Appl. No. 11/297,567, filed Dec. 8, 2005.
Ahn, Kie Y., “Lanthanum Aluminum Oxynitride Dielectric Films”, U.S. Appl. No. 11/216,474, filed Aug. 31, 2005.
Ahn, Kie Y., et al., “Magnesium Titanium Oxide Films”, U.S. Appl. No. 11/189,075, filed Jul. 25, 2005.
Ahn, Kie Y., “Magnesium-Doped Zinc Oxide Structures and Methods”, U.S. Appl. No. 11/706,820, filed Feb. 13, 2007.
Ahn, Kie Y., et al., “Methods to Form Dielectric Structures in Semiconductor Devices and Resulting Devices”, U.S. Appl. No. 11/581,675, filed Aug. 16, 2006.
Ahn, Kie Y., “Molybdenum-Doped Indium Oxide Structures and Methods”, U.S. Appl. No. 11/706,944, filed Feb. 13, 2007.
Ahn, Kie Y., “Titanium Aluminum Oxide Films”, U.S. Appl. No. 11/566,042, filed Dec. 1, 2006, 48 pgs.
Ahn, Kie Y., et al., “Tungsten-Doped Indium Oxide Structures and Methods”, U.S. Appl. No. 11/706,498, filed Feb. 13, 2007.
Ahn, Kie Y., “Zirconium-Doped Gadolinium Oxide Films”, U.S. Appl. No. 11/215,578, filed Aug. 29, 2005.
Ahn, Kie Y., et al., “Zirconium-Doped Zinc Oxide Structures and Methods”, U.S. Appl. No. 11/707,173, filed Feb. 13, 2007.
Alen, Petra , “Atomic Layer deposition of Ta(AI)N(C) thin films using trimethylaluminum as a reducing agent”, Journal of the Electrochemical Society, 148(10), (Oct. 2001), G566-G571.
Asai, S. , “Technology Challenges for Integration Near and Below 0.1 micrometer”, Proceedings of the IEEE, 85(4), Special Issue on Nanometer-Scale Science & Technology,(Apr. 1997),505-520.
Auberton-Herve, A. J., “SOI: Materials to Systems”, Digest of the International Electron Device Meeting, San Francisco,(Dec. 1996),3-10.
Banerjee, S. , “Applications of silicon-germanium-carbon in MOS and bipolar transistors”, Proceedings of the SPIE—The International Society for Optical Engineering, 3212, (1997),118-128.
Banerjee, S. K., et al., “Characterization of Trench Transistors for 3-D Memories”, 1986 Symposium on VLSI Technology, Digest of Technical Papers, San Diego, CA, (May 1986),79-80.
Beensh-Marchwicka, G. , et al., “Preparation of thermosensitive magnetron sputtered thin films”, Vacuum, 53(1-2), (May 1999),47-52.
Bendoraitis, J G., et al., “Optical energy gaps in the monoclinic oxides of hafnium and zirconium and their solid solutions”, Journal of Physical Chemistry, 69(10), (1965),3666-3667.
Bengtsson, Stefan , et al., “Interface charge control of directly bonded silicon structures”, J. Appl. Phys., 66(3), (Aug. 1989),1231-1239.
Blalock, T. N., et al., “A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier”, IEEE Journal of Solid-State Circuits, 27(4), (Apr. 1992),pp. 618-624.
Bomchil, G. , “Porous Silicon: The Material and its Applications in Silicon-On-Insulator Techologies”, Applied Surface Science, 41/42, (1989),604-613.
Braud, F. , “Ultra Thin Diffusion Barriers for Cu Interconnections at The Gigabit Generation and Beyond”, VMIC Conference Proceedings, (1996),174-179
Bright, A A., et al., “Low-rate plasma oxidation of Si in a dilute oxygen/helium plasma for low-temperature gate quality Si/SiO2 interfaces”, Applied Physics Letters, 58(6), (Feb. 1991),619-621.
Bunshah, Rointan F., et al., “Deposition Technologies for Films and Coatings: Developments and Applications”, Park Ridge, N.J., U.S.A. : Noyes Publications, (1982),102-103.
Burnett, D. , “Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits”, 1994 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, (Jun. 1994), 15-16.
Burnett, D. , “Statistical Threshold-Voltage Variation and its Impact on Supply-Voltage Scaling”, Proceedings SPIE: Microelectronic Device and Multilevel Interconnection Technology, 2636, (1995),83-90.
Callegari, A. , et al., “Physical and electrical characterization of Hafnium oxide and Hafnium silicate sputtered films”, Journal of Applied Physics, 90(12), (Dec. 15, 2001),6466-75.
Cartagena, E , et al., “Bonded Etchback Silicon on Sapphire Bipolar Junction Transistors”, Extended Abstracts—Electrochemical Society(1), Program and Abstracts: 183rd Meeting of the Electrochemical Society, Pennington, NJ,(1993),191.
Cava, R. J., et al., “Improvement of the dielectric properties of Ta2O5 through substitution with AI2O3”, Applied Physics Letters, 70(11), (Mar. 1997),1396-8.
Chang, Hyo S., et al., “Excellent thermal stability of AI2O3/ZrO2/AI2O3 stack structure of metal-oxide-semiconductor gate dielectrics application”, Applied Physics Letters, 80(19), (May 6, 2002),3385-7.
Chen, M. J., et al., “Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Cicuits”, IEEE Transactions on Electron Devices, 43, (Jun. 1996),904-909.
Chen, M. J., et al., “Optimizing the Match in Weakly Inverted MOSFET's by Gated Lateral Bipolar Action”, IEEE Transactions on Electron Devices, 43, (May 1996),766-773.
Chen, P. J., et al., “Thermal stability and scalability of Zr-aluminate-based high-k gate stacks”, Symposium on VLSI Technology Digest, (2002),192-3.
Cheng, Baohong , et al., “The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100nm MOSFET's”, IEEE Transactions on Electron Devices, 46(7), (Jul. 1999),1537-1544.
Chesler, R. , et al., “Solid-State Ionic Lasers”, In: Laser Handbook, vol. 1, Arecchi, F.T., et al., (eds.), North-Holland Publishing Company, Amsterdam,(1972),p. 353.
Chin, A. , et al., “High Quality La2O3 and AI2O3 Gate Dielectrics with Equivalent Oxide Thickness 5-10A”, Digest of Technical Papers. 2000 Symposium on VLSI Technology, 2000, Honolulu,(Jun. 13-15, 2000),16-17.
Chung, I. Y., et al., “A New SOI Inverter for Low Power Applications”, Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL,(1996),20-21.
Clark, P , “IMEC Highlights Hafnium, Metal Gates for High-k Integration”, Semiconductor Business News, at Silicon Strategies.com, (Oct. 11, 2002),2 pages.
Colombo, D. , et al., “Anhydrous Metal Nitrates as Volatile Single Source Precursors for the CVD of Metal Oxide Films”, Communications, Department of EE, U of M, Mpls, MN, (Jul. 7, 1998),3 pages.
Conley, Jr., J. F., et al., “Atomic Layer Deposition of Hafnium Oxide Using Anhydrous Hafnium Nitrate”, Electrochemical and Solid-State Letters, 5(5), (2002),C57-C59.
Copel, M. , et al., “Formation of a stratified lanthanum silicate dielectric by reaction with Si(001)”, Applied Physics Letters, 78(11), (Mar. 12, 2001),1607-1609.
Copel, M. , et al., “Structure and stability of ultrathin zirconium oxide layers on Si(001)”, Applied Physics Letters, 76(4), (Jan. 2000),436-438.
Da Rosa, E B., et al., “Annealing of ZrAIxOy ultrathin films on Si in a vacuum or in O2”, Journal of the Electrochemical Society, 148 (12), (Dec. 2001),G695-G703.
Dalal, Vikram L., et al., “Microcrystalline Germanium Carbide—A new material for PV conversion”, Presented at 2001 NCPV Program Review Meeting, (2001),348-349.
De, V. K., “Radom MOSFET Parameter Fluctuation Limits to Gigascale Integration (GSI)”, 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, (Jun. 11-13, 1996),198-199.
De Flaviis, Franco , et al., “Planar microwave integrated phase-shifter design with high purity ferroelectric material”, IEEE Transactions on Microwave Theory & Techniques, 45(6), (Jun. 1997),963-969.
Denton, Jack P., et al., “Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate”, IEEE Electron Device Letters, 17(11), (Nov. 1996),509-511.
Desu, S B., “Minimization of Fatigue in Ferroelectric Films”, Physica Status Solidi A, 151(2), (1995),467-480.
Dimoulas, A. , et al., “Structural and electrical quality of the high-k dielectric Y2O3 on Si (001): Dependence on growth parameters”, Journal of Applied Physics, 92(1), (Jul. 1, 2002),426-431.
Ding, “Copper Barrier, Seed Layer and Planarization Technologies”, VMIC Conference Proceedings, (1997),87-92.
Ducso, C , et al., “Deposition of tin oxide into porous silicon by atomic layer epitaxy”, Journal of the Electrochemical Society, 143, (1996),683-687.
El-Kareh, B , et al., “The evolution of DRAM cell technology”, Solid State Technology, 40(5), (1997),89-90, 92, 95-6, 98, 100-1.
Engelhardt, M. , “Modern Applications of Plasma Etching and Patterning in Silicon Process Technology”, Contributions to Plasma Physics, 39(5), (1999),473-478.
Fong, Y. , “Oxides Grown on Textured Single-Crystal Silicon—Dependence on Process and Application in EEPROMs”, IEEE Transactions on Electron Devices, 37(3), (Mar. 1990),583-590.
Forbes, “Hafnium Aluminum Oxynitride High-K Dielectric and Metal Gates”, U.S. Appl. No. 11/514,558, filed Aug. 31, 2006.
Forbes, “Hafnium Tantalum Oxynitride High-K Dielectric and Metal Gates”, U.S. Appl. No. 11/515,114, filed Aug. 31, 2005.
Forbes, L. , et al., “Resonant Forward-Biased Guard-Ring Diodes for Suppression of Substrate Noise in Mixed-Mode CMOS Circuits”, Electronics Letters, 31, (Apr. 1995),720-721.
Forbes, Leonard , et al., “Silicon Lanthanide Oxynitride Films”, U.S. Appl. No. 11/514, 533, filed Aug. 31, 2006.
Forbes, et al., “Tantalum Aluminum Oxynitride High-K Dielectric and Metal Gates”, U.S. Appl. No. 11/514,655, filed Aug. 31, 2006.
Forbes, Leonard , et al., “Tantalum Silicon Oxynitride High-K Dielectrics and Metal Gates”, U.S. Appl. No. 11/514,601, filed Aug. 31, 2006.
Forsgren, Katarina, “Atomic Layer Deposition of HfO2 using hafnium iodide”, Conference held in Monterey, California, (May 2001), 1 page.
Forsgren, Katarina, “CVD and ALD of Group IV- and V-Oxides for Dielectric Applications”, Comprehensive Summaries of Uppsala Dissertation from the Faculty of Science and Technology, 665, (2001).
Foster, R. , et al., “High Rate Low-Temperature Selective Tungsten”, In: Tungsten and Other Refractory Metals for VLSI Applications III, V.A. Wells, ed., Materials Res. Soc., Pittsburgh, PA,(1988),69-72.
Fuse, Tsuneaki , et al., “A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic”, 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, (1997),286-287.
Fuyuki, Takashi , et al., “Electronic Properties of the Interface between Si and TiO2 Deposited at Very Low Temperatures”, Japanese Journal of Applied Physics, Part 1 (Regular Papers & Short Notes), 25(9), (September 1986),1288-1291.
Fuyuki, Takashi , et al., “Initial stage of ultra-thin SiO2 formation at low temperatures using activated oxygen”, Applied Surface Science, 117-118, (Jun. 1997),123-126.
Gagliano, F. P., et al., “Laser Processing Fundamentals”, In Lasers in Industry, edited by S.S. Charschan, Van Nostrand Reinhold Company,(1972),156-164.
Gartner, M. , et al., “Spectroellipsometric characterization of lanthanide-doped TiO2 films obtained via the sol-gel technique”, Thin Solid Films, 234(1-2), (1993),561-565.
Gartner, M , “Spectroellipsometric characterization of lanthanide-doped TiO2 films obtained via the sol-gel technique”, Thin Solid Films, 234(1-2), (1993),561-565.
Geller, S. , et al., “Crystallographic Studies of Perovskite-like Compounds. II. Rare Earth Aluminates”, Acta Cryst., 9, (May 1956),1019-1025.
Giess, E. A., et al., “Lanthanide gallate perovskite-type substrates for epitaxial, high-Tc superconducting Ba2YCu3O7-δfilms”, IBM Journal of Research and Development, 34(6), (Nov. 1990),916-926.
Gong, S. , “Techniques for reducing switching noise in high speed digital systems”, Proceedings Eighth Annual IEEE International ASIC Conference and Exhibit, (1995),21-24.
Gosele, U. , et al., “Self-propagating Room-temperature Silicon Wafer Bonding in Ultrahigh Vacuum”, Applied Physics Letters, 67(24), (Dec. 11, 1995),3614-3616.
Guha, S , et al., “Atomic beam deposition of lanthanum-and yttrium-based oxide thin films for gate dielectrics”, Applied Physics Letters, 77, (2000),2710-2712.
Guillaumot, B , et al., “75 nm damascene metal gate and high-k integration for advanced CMOS devices”, Technical Digest of International Electron Devices Meeting 2002, (2002),355-358.
Guo, Xin , et al., “High quality ultra-thin (1.5 nm) TiO2-Si3N4 gate dielectric for deep sub-micron CMOS technology”, IEDM Technical Digest. International Electron Devices Meeting, (Dec. 5-8, 1999),137-140.
Gusev, E P., “Ultrathin High-K Dielectrics Grown by Atomic Layer Deposition: A Comparative Study of ZrO2, HfO2, Y2O3 and AI2O3”, Electrochemical Society Proceedings vol. 2001-9, (2001),189-195.
Gutowski, M J., “Thermodynamic stability of high-K dielectric metal oxides ZrO2 and HfO2 in contact with Si and SiO2”, Applied Physics Letters, 80(11), (Mar. 18, 2002),1897-1899.
Hao, M. Y., “Electrical Characteristics of Oxynitrides Grown on Textured Single-Crystal Silicon”, Applied Physics Letters, 60, (Jan. 1992),445-447.
Harada, M. , “Suppression of Threshold Voltage Variation in MTCMOS/SIMOX Circuit Operating Below 0.5 V”, 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, (Jun. 11-13, 1996),96-97.
Harendt, Christine, “Silicon on Insulator Material by Wafer Bonding”, Journal of Electronic Materials, 20(3), (Mar. 1991),267-77.
Hayashi, H. , et al., “Fabrication of Low-temperature bottom-gate Poly-Si TFTs on large-area substrate by linear-beam excimer laser crystallization and ion doping method”, IEEE IEDM, vol. 95, (1995),829-832.
Heavens, O. , “Optical Properties of Thin Solid Films”, Optical Properties of Thin Solid Films, Dover Pubs. Inc., New York,(1965),155-206.
Herrold, J. , et al., “Growth and properties of microcrystalline germanium-carbide alloys”, Amorphous and Heterogeneous Silicon Thin films: Fundamentals to Devices—1999 Symposium, San Francisco, CA, Apr. 5-9, 1999,(1999),16 pgs.
Herrold, J. , et al., “Growth and properties of microcrystalline germanium-carbide alloys grown using electron cyclotron resonance plasma processing”, Journal of Non-Crystalline Solids (Netherlands), 270(1-3), (May 2000),255-259.
Hirayama, Masaki , et al., “Low-Temperature Growth of High-Integrity Silicon Oxide Films by Oxygen Radical Generated in High Density Krypton Plasma”, International Electron Devices Meeting 1999. Technical Digest, (1999),249-252.
Hisamoto, D. , et al., “A New Stacked Cell Structure for Giga-Bit DRAMs using Vertical Ultra-Thin SOI (Delta) MOSFETs”, 1991 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C.,(Dec. 8-11, 1991),959-961.
Hodges, David A., et al., “MOS Decoders”, In: Analysis and Design of Digital Integrated Circuits, 2nd Edition, Section: 9.1.3,(1988),354-357.
Holman, W. T., et al., “A Compact Low Noise Operational Amplifier for a 1.2 Micrometer Digital CMOS Technology”, IEEE Journal of Solid-State Circuits, 30, (Jun. 1995),710-714.
Horiuchi, M , et al., “A mechanism of silicon wafer bonding”, of the First International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications, (1992),48-62.
Hoshino, Y. , et al., “Characterization and Control of the HfO2/Si(001) Interfaces”, Applied Physics Letters, 81, (Sep. 30, 2002),2650-2652.
Hoshino, Y. , “Characterization and Control of the HfO2/Si(001) Interfaces”, Applied Physics Letters, 81, (Sep. 30, 2002),2650-2652.
Hu, G. , “Will Flash Memory Replace Hard Disk Drive?”, 1994 IEEE International Electron Device Meeting, Panel Discussion, Session 24, Outline,(Dec. 1994),2 pages.
Huang, C. H., et al., “La2O3/Si0.3Ge0.7 p-MOSFETs with high hole mobility and good device characteristics”, IEEE Electron Device Letters, 23 (12), (Dec. 2002),710-712.
Huang, W. L., et al., “TFSOI Complementary BiCMOS Technology for Low Power Applications”, IEEE Transactions on Electron Devices, 42, (Mar. 1995),506-512.
Hubbard, K. J., et al., “Thermodynamic stability of binary oxides in contact with silicon”, Journal of Materials Research, 11(11), (Nov. 1996),2757-2776.
Hunt, C. E., et al., “Direct bonding of micromachined silicon wafers for laser diode heat exchanger applications”, Journal of Micromechanics and Microengineering, 1(3), (Sep. 1991),152-156.
Iddles, D M., et al., “Relationships between dopants, microstructure and the microwave dielectric properties of ZrO2-TiO2-SnO2 ceramics”, Journal of Materials Science, 27(23), (Dec. 1992),6303-6310.
Iijima, T. , “Microstructure and Electrical Properties of Amorphous W-Si-N Barrier Layer for Cu Interconnections”, 1996 VMIC Conference, (1996),168-173.
Imthurn, George P., et al., “Bonded Silicon-on-Sapphire Wafers and Devices”, Journal of Applied Physics, 72(6), (Sep. 1992),2526-7.
Iwai, H. , et al., “Advanced gate dielectric materials for sub-100 nm CMOS”, International Electron Devices Meeting, 2002. IEDM '02, Digest., (Dec. 8-11, 2002),625-628.
Jeon, Sanghun , et al., “Excellent electrical characteristics of Ianthanide (Pr, Nd, Sm, Gd, and Dy) oxide and lanthanide-doped oxide for MOS gate dielectric applications”, Electron Devices Meeting, 2001. IEDM Technical Digest. International, (2001),471-474.
Jeon, Sanghun , et al., “Ultrathin nitrided-nanolaminate (AI2O3/ZrO2/AI2O3) for metal-oxide-semiconductor gate dielectric applications”, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 20(3), (May 2002),1143-5.
Jeong, Chang-Wook , et al., “Plasma-Assisted Atomic layer Growth of High-Quality Aluminum Oxide Thin Films”, Japanese Journal of Applied Physics, 40, (Jan. 2001),285-289.
Jun, Y. K., “The Fabrication and Electrical Properties of Modulated Stacked Capacitor for Advanced DRAM Applications”, IEEE Electron Device Letters, 13, (Aug. 1992),430-432.
Jung, T. S., “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications”, IEEE Journal of Solid-State Circuits, 31, (Nov. 1996), 1575-1583.
Jung, H S., et al., “Improved current performance of CMOSFETs with nitrogen incorporated HfO2-AI2O3 laminate gate dielectric”, Technical Digest of International Electron Devices Meeting 2002, (2002),853-856.
Kang, H. K., et al., “Highly Manufacturable Process Technology for Reliable 256 Mbit and 1 Gbit DRAMs”, IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA,(Dec. 11-14, 1994),635-638.
Kang, L , et al., “MOSFET devices with polysilicon on single-layer HfO2 high-K dielectrics”, International Electron Devices Meeting 2000. Technical Digest. IEDM, (2000),35-8.
Kawai, Y , et al., “Ultra-low-temperature growth of high-integrity gate oxide films by low-energy lon-assisted oxidation”, Applied Physics Letters, 64(17), (Apr. 1994),2223-2225.
Keomany, D. , et al., “Sol gel preparation of mixed cerium-titanium oxide thin films”, Solar Energy Materials and Solar Cells, 33(4), (Aug. 1994),429-441.
Kim, Y W., et al., “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications”, Technical Digest of International Electron Devices Meeting 2002, (2002),69-72.
Kim, Y. S., “A Study on Pyrolysis DMEAA for Selective Deposition of Aluminum”, In: Advanced Metallization and Interconnect Systems for ULSI Applications in 1995, R.C. Ellwanger, et al., (eds.), Materials Research Society, Pittsburgh, PA,(1996),675-680.
Kim, C. T., et al., “Application of AI2O3 Grown by Atomic Layer Deposition to DRAM and FeRam”, International Symposium in Integrated Ferroelectrics, (Mar. 2000),316.
Kim, D. , et al., “Atomic Control of Substrate Termination and Heteroepitaxial Growth of SrTiO3/LaAIO3 Films”, Journal of the Korean Physical Society, 36(6), (Jun. 2000),444-448.
Kim, Byoung-Youp , et al., “Comparison study for TiN films deposited from different method: chemical vapor deposition and atomic layer deposition”, Mechanisms of Surface and Microstructure Evolution in Deposited Films and Film Structures Symposium (Materials Research Society Symposium Proceedings vol. 672), (2001),7.8.1-7.8.6.
Kim, Taeseok , et al., “Correlation between strain and dielectric properties in ZrTiO4 thin films”, Applied Physics Letters, 76(21), (May 2000),3043-3045.
Kim, Taeseok , et al., “Dielectric properties and strain analysis in paraelectric ZrTiO4 thin films deposited by DC magnetron sputtering”, Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 39(7A), (2000),4153-4157.
Kim, Yongjo , et al., “Effect of microstructures on the microwave dielectric properties of ZrTiO4 thin films”, Applied Physics Letters, 78(16), (Apr. 16, 2001),2363-2365.
Kim, Y. , et al., “Substrate dependence on the optical properties of AI2O3 films grown by atomic layer deposition”, Applied Physics Letters, 71(25 ), (Dec. 22, 1997),3604-3606.
Kim, Y , “Substrate dependence on the optical properties of AI2O3 films grown by atomic layer deposition”, Applied Physics Letters, vol. 71, No. 25, (Dec. 22, 1997),3604-3606.
Kishimoto, T. , et al., “Well Structure by High-Energy Boron Implantation for Soft-Error Reduction in Dynamic Random Access Memories (DRAMs)”, Japanese Journal of Applied Physics, 34, (Dec. 1995),6899-6902.
Kohyama, Y. , et al., “Buried Bit-Line Cell for 64MB DRAMs”, 1990 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, (Jun. 4-7, 1990),17-18.
Koshida, N. , “Efficient Visible Photoluminescence from Porous Silicon”, Japanese Journal of Applied Physics, 30, (Jul. 1991),L1221-L1223.
Kouvetakis, J. , et al., “Novel chemical routes to silicon-germanium-carbon materials”, Applied Physics Letters, 65(23), (Dec. 5, 1995),2960-2962.
Krauter, G. , et al., “Room Temperature Silicon Wafer Bonding with Ultra-Thin Polymer Films”, Advanced Materials, 9(5), (1997),417-420.
Kuge, Shigehiro , et al., “SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories”, IEEE Journal of Solid-State Circuits, 31(4), (Apr. 1996),pp. 586-591.
Kukli, Kaupo , “Atomic Layer Deposition of Titanium Oxide TiI4 and H2O2”, Chemical Vapor Deposition, 6(6), (2000),303-310.
Kukli, Kaupo , “Comparison of hafnium oxide films grown by atomic layer deposition from iodide and chloride precursors”, Thin Solid Films, 416, (2002),72-79.
Kukli, K. , et al., “Controlled growth of yttrium oxysulphide thin films by atomic layer deposition”, Materials Science Forum, 315-317, (1999),216-221.
Kukli, Kaupo , “Dielectric Properties of Zirconium Oxide Grown by Atomic Layer Deposition from Iodide Precursor”, Journal of The Electrochemical Society, 148(12), (2001),F227-F232.
Kukli, Kaupo , et al., “Influence of thickness and growth temperature on the properties of zirconium oxide films growth by atomic layer deposition on silicon”, Thin Solid Films, 410(1-2), (2002),53-60.
Kukli, Kaupo , “Low-Temperature Deposition of Zirconium Oxide-Based Nanocrystalline Films by Alternate Supply of Zr[OC(CH3)3]4 and H2O”, Chemical Vapor Deposition, 6(6), (2000),297-302.
Kukli, K J., et al., “Properties of hafnium oxide films grown by atomic layer deposition from hafnium tetraiodide and oxygen”, Journal of Applied Physics, 92(10), (Nov. 15, 2002),5698-5703.
Kwo, J. , et al., “High E gate dielectrics Gd2O3 and Y2O3 for silicon”, Applied Physics Letters, 77(1), (Jul. 3, 2000),130-132.
Lantz, Il, L. , “Soft Errors Induced By Alpha Particles”, IEEE Transactions on Reliability, 45, (Jun. 1996),174-179.
Lasky, J. B., “Wafer Bonding for Silicon-on-Insulator Technologies”, Applied Physics Letters, 48(1), (Jan. 6, 1986),78-80.
Laursen, T. , “Encapsulation of Copper by Nitridation of Cu-Ti Alloy/Bilayer Structures”, International Conference on Metallurgical Coatings and Thin Films, Abstract No. H1.03, San Diego, CA,(Apr. 1997),309.
Lee, Byoung H., et al., “Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8 A-12 A)”, Electron Devices Meeting, 2000. IEDM Technical Digest. International, (2000),39-42.
Lee, A E., et al., “Epitaxially grown sputtered LaAIO3 films”, Applied Physics Letters, 57(19), (Nov. 1990),2019-2021.
Lee, S. J., et al., “Hafnium oxide gate stack prepared by in situ rapid thermal chemical vapor deposition process for advanced gate dielectrics”, Journal of Applied Physics, 92 (5), (Sep. 1, 2002),2807-09.
Lee, S J., “High quality ultra thin CVD HfO2 gate stack with poly-Si gate electrode”, Electron Devices Meeting, 2000. IEDM Technical Digest. International, (2000),31-34.
Lee, Cheng-Chung , et al., “Ion-assisted deposition of silver thin films”, Thin Solid Films, 359,(2000),pp. 95-97.
Lee, Jung-Hyoung , et al., “Mass production worthy HfO2-Al2O3 laminate capacitor technology using Hf liquid precursor for sub-100 nm DRAMs”, International Electron Devices Meeting, 2002. IEDM '02. Digest., (Dec. 8-11, 2002),221-224.
Lee, Dong H., et al., “Metalorganic chemical vapor deposition of TiO2:N anatase thin film on Si substrate”, Appl. Phys. Lett., 66(7), (Feb. 1995),815-816.
Lee, L P., et al., “Monolithic 77 K dc Squid magnetometer”, Applied Physics Letters, 59(23), (Dec. 1991),3051-3053.
Lee, C. H., “MOS Characteristics of Ultra Thin Rapid Thermal CVD ZrO2 and Zr Silicate Gate Dielectrics”, Electron Devices Meeting, 2000. IEDM Technical Digest. International, (2000),27-30.
Lee, C H., et al., “MOS Devices with High Quality Ultra Thin CVD ZrO2 Gate Dielectrics and Self-Aligned TaN and TaN/Poly-Si Gate electrodes”, 2001 Symposium on VLSI, Technology Digest of Technical Papers, (2001),137-138.
Lee, B. H., et al., “Novel Pattern Transfer Process for Bonded SOI Giga-bit DRAMs”, IEEE International SOI Conference, Piscataway, NJ,(1996),114-115.
Lee, Byoung H., et al., “Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate Dielectric Application”, Technical Digest of IEDM, (1999),133-136.
Lehmann, V. , “The Physics of Macropore Formation in Low Doped n-Type Silicon”, Journal of the Electrochemical Society, 140(10), (Oct. 1993),2836-2843.
Leskela, M. , “ALD precursor chemistry: Evolution and future challenges”, J. Phys. IV France, 9, (1999),837-852.
Liu, C. T., “Circuit Requirement and Integration Challenges of Thin Gate Dielectrics for Ultra Small MOSFETs”, International Electron Devices Meeting 1998. Technical Digest, (1998),747-750.
Liu, Y C., et al., “Growth of ultrathin SiO2 on Si by surface irradiation with an O2+Ar electron cyclotron resonance microwave plasma at low temperatures”, Journal of Applied Physics, 85(3), (Feb. 1999),1911-1915.
Lopez, E. , et al., “Laser assisted integrated processing of SiGeC films on silicon”, Thin Solid Films, vol. 453-454, (Apr. 1, 2004),46-51.
Lu, D, , “Bonding Silicon Wafers by Use of Electrostatic Fields Followed by Rapid Thermal Heating”, Materials Letters, 4(11), (Oct. 1986),461-464.
Lu, N. , et al., “The SPT Cell—A New Substrate-Plate Trench Cell for DRAMs”, 1985 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C.,(Dec. 1-4, 1985),771-772.
Luan, et al., “High Quality Ta2O5 Gate Dielectrics and T [. . . ]”, IEEE Technical Digest of Int. Elec. Devices Mtng 1999, (1999),141-142.
Lucovsky, G , et al., “Microscopic model for enhanced dielectric constants in low concentration SiO2-rich noncrystalline Zr and Hf silicate alloys”, Applied Physics Letters, 77(18), (Oct. 2000),2912-2914.
Luo, Z J., et al., “Ultra-thin ZrO2 (or Silicate) with High Thermal Stability for CMOS Gate Applications”, 2001 Symposium on VLSI Technology Digest of Technical Papers, (2001),135-136.
MacSweeney, D. , et al., “Modelling of Lateral Bipolar Devices in a CMOS Process”, IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN,(Sep. 1996),27-30.
Maeda, S. , et al., “A Vertical Phi-Shape Transistor (VPhiT) Cell for 1Gbit DRAM and Beyond”, 1994 Symposium of VLSI Technology, Digest of Technical Papers, Honolulu, HI,(Jun. 7-9, 1994),133-134.
Maeda, S. , et al., “Impact of a Vertical Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond”, IEEE Transactions on Electron Devices, 42, (Dec. 1995),2117-2123.
Malaviya, S. , “Dynamic Semiconductor RAM Structures”, IBM TBD, 15, (Jul. 1972),p. 42.
Maria, J. P., et al., “High temperature stability in Ianthanum and zirconia-based gate dielectrics”, Journal of Applied Physics, 90(7), (Oct. 1, 2001),3476-3482.
Martin, P J., et al., “Ion-beam-assisted deposition of thin films”, Applied Optics, 22(1), (Jan. 1983),178-184.
Masu, K. , et al., “Multilevel Metallization Based on AI CVD”, 1996 IEEE Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI,(Jun. 11-13, 1996),44-45.
McCredie, B. D., et al., “Modeling, Measurement, and Simulation of Simultaneous Switching Noise”, IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, 19, (Aug. 1996),461-472.
Michaelson, Herbert B., “The work function of the elements and its periodicity”, Journal of Applied Physics, 48(11), (Nov. 1977),4729-4733.
Molodyk, A A., et al., “Volatile Surfactant-Assisted MOCVD: Application to LaAIO3 Thin Film Growth ”, Chemical Vapor Deposition, 6(3), (Jun. 2000),133-138.
Molsa, Heini , et al., “Growth of yttrium oxide thin films from beta -diketonate precursor”, Advanced Materials for Optics and Electronics, 4(6), (Nov.-Dec. 1994),389-400.
Muller, D. A., et al., “The Electronic Structure at the Atomic Scale of Ultrathin Gate Oxides”, Nature, 399, (Jun. 1999),758-761.
Mumola, P. B., et al., “Recent Advances in Thinning of Bonded SOI Wafers by Plasma Assisted Chemical Etching”, Electrochemical Society Proceedings, 95-7, (1995),28-32.
Nakagawara, Osamu , et al., “Electrical properties of (Zr, Sn)TiO4 dielectric thin film prepared by pulsed laser deposition”, Journal of Applied Physics, 80(1), (Jul. 1996),388-392.
Nakajima, Anri, “Atomic-layer deposition of ZrO2 with a Si nitride barrier layer”, Applied Physics Letters, 81(15), (Oct. 2002),2824-2826.
Nakajima, et al., “Atomic-layer-deposited silicon-nitride/SiO2 stacked gate dielectrics for highly reliable p-metal-oxide-semiconductor filed-effect transistors”, Applied Physics Letters, vol. 77, (Oct. 2000),2855-2857.
Nakajima, Anri , et al., “NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability”, Applied Physics Letters, 80(7), (Feb. 2002),1252-1254.
Nakajima, Anri, “Soft breakdown free atomic-layer-deposited silicon-nitride/SiO2 stack gate dielectrics”, International Electron Devices Meeting. Technical Digest, (2001),6.5.1-4.
Nakamura, et al., “Giga-bit DRAM Cells with Low Capacitance and Low Resistance Bit-Lines on Buried MOSFET's and Capacitors by Using Bonded SOI Technology—Reversed-Stacked-Capacitor (RSTC) Cell-”, Technical Digest—International Electron Devices Meeting, (1995),889-892.
Neumayer, D A., et al., “Materials characterization of ZrO2-SiO2 and HfO2-SiO2 binary oxides deposited by chemical solution deposition”, Journal of Applied Physics, 90(4), (Aug. 15, 2001),1801-1808.
Nieminen, Minna , et al., “Formation and stability of lanthanum oxide thin films deposited from B-diketonate precursor”, Applied Surface Science, 174(2), (Apr. 16, 2001),155-165.
Niilisk, A , “Atomic-scale optical monitoring of the initial growth of TiO2 thin films”, Proceedings of the SPIE—The International Society for Optical Engineering, 4318, (2001),72-77.
Nitayama, A. , et al., “High Speed and Compact CMOS Circuits with Multipillar Surrounding Gate Transistors”, IEEE Transactions on Electron Devices, 36, (Nov. 1989),2605-2606.
Oates, D E., et al., “Surface impedance measurements of YBa2Cu3O7-x thin films in stripline resonators”, IEEE Transactions on Magnetics, vol. 27, No. 2, pt.2, (Mar. 1991),867-871.
Oh, C B., et al., “Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications”, Technical Digest of International Electron Devices Meeting 2002, (2002),423-426.
Ohba, T. , et al., “Evaluation on Selective Deposition of CVD W Films by Measurement of Surface Temperature”, In: Tungsten and Other Refractory Metals for VLSI Applications II, Materials Research Society, Pittsburgh, PA,(1987),59-66.
Ohba, T. , et al., “Selective Chemical Vapor Deposition of Tungsten Using Silane and Polysilane Reductions” , In: Tungsten and Other Refractory Metals for VLSI Applications IV, Materials Research Society, Pittsburgh, PA,(1989),17-25.
Ohmi, S. , et al., “Rare Earth Metal Oxides for High-K Gate Insulator”, Electrochemical Society Proceedings, vol. 2002-2, (2002),376-387.
Ohno, Y. , et al., “Estimation of the Charge Collection for the Soft-Error Immunity by the 3D-Device Simulation and the Quantitative Investigation”, Simulation of Semiconductor Devices and Processes, 6, (Sep. 1995),302-305.
Ohring, Milton , “The Materials Science of Thin Films”, Boston : Academic Press, (1992),118,121,125.
Oowaki, Y. , et al., “New alpha-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell”, IEICE Transactions on Electronics, 78-C, (Jul. 1995),845-851.
Oshida, S. , et al., “Minority Carrier Collection in 256 M-bit DRAM Cell on Incidence of Alpha-Particle Analyzed by Three-Dimensional Device Simulation”, IEICE Transactions on Electronics, 76-C, (Nov. 1993),1604-1610.
Osten, H J., et al., “High-k Gate Dielectrics with Ultra-low Leakage Current Based on Praseodymium Oxide”, Technical Digest of IEDM, (2000),653-656.
Ozaki, T. , et al., “A Surrounding Isolation-Merged Plate Electrode (Simple) Cell with Checkered Layout for 256Mbit DRAMs and Beyond”, 1991 IEEE International Electron Devices Meeting, Washington, D.C.,(Dec. 8-11, 1991),469-472.
Pan, Tung M., et al., “High quality ultrathin CoTiO3 high-k gate dielectrics”, Electrochemical and Solid-State Letters, 3(9), (Sep. 2000),433-434.
Pan, Tung M., et al., “High-k cobalt-titanium oxide dielectrics formed by oxidation of sputtered Co/Ti or Ti/Co films”, Applied Physics Letters, 78(10), (Mar. 5, 2001),1439-1441.
Park, Jaehoo , et al., “Chemical vapor deposition of HfO2 thin films using a novel carbon-free precursor: characterization of the interface with the silicon substrate”, Journal of the Electrochemical Society, 149(1), (2002),G89-G94.
Park, Byung-Eun , et al., “Electrical properties of LaAIO3/Si and Sr0.8Bi2.2Ta2O9/LaAIO3/Si structures”, Applied Physics Letters, 79(6), (Aug. 2001),806-808.
Park, Byoung K., et al., “Interfacial reaction between chemically vapor-deposited HfO2 thin films and a HF-cleaned Si substrate during film growth and postannealing”, Applied Physics Letters, 80(13), (Apr. 1, 2002),2368-70.
Parke, S. A., et al., “A High-Performance Lateral Bipolar Transistor Fabricated on SIMOX”, IEEE Electron Device Letters, 14, (Jan. 1993),33-35.
Pein, H. , “A 3-D Sidewall Flash EPROM Cell and Memory Array”, IEEE Transactions on Electron Devices, 40, (Nov. 1993),2126-2127.
Pein, H. , “Performance of the 3-D Pencil Flash EPROM Cell and Memory Array”, IEEE Transactions on Electron Devices, 42, (Nov. 1995),1982-1991.
Pein, H. B., “Performance of the 3-D Sidewall Flash EPROM Cell”, IEEE International Electron Devices Meeting, Technical Digest, (1993),11-14.
Perkins, Charles M., et al., “Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition”, Applied Physics Letters, 78(16), (Apr. 2001),2357-2359.
Poveshchenko, V P., et al., “Investigation of the phase composition of films of zirconium, hafnium and yttrium oxides”, Soviet Journal of Optical Technology , 51(5), (1984),277-279.
Qi, Wen-Jie , et al., “MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si”, Electron Devices Meeting, 1999. IEDM Technical Digest. International, (1999),145-148.
Qi, Wen-Jie , et al., “Performance of MOSFETs with ultra thin ZrO2 and Zr silicate gate dielectrics”, 2000 Symposium on VLSI Technology. Digest of Technical Papers, (2000),40-41.
Rahtu, Antti , “Atomic Layer Deposition of Zirconium Titanium Oxide from Titanium Isopropoxide and Zirconium Chloride”, Chemistry of Materials, 13(5), (May 2001),1528-1532.
Ramakrishnan, E S., et al., “Dielectric properties of radio frequency magnetron sputter deposited zirconium titanate-based thin films”, Journal of the Electrochemical Society, 145(1), (Jan. 1998),358-362.
Ramm, J. , et al., “Hydrogen cleaning of silicon wafers. Investigation of the wafer surface after plasma treatment”, Thin Solid Films, 228, (1993),23-26.
Ramo, S. , Fields and Waves in Communication Electronics, Third Edition, John Wiley & Sons, Inc,(1994),428-433.
Rao, K. V., et al., “Trench Capacitor Design Issues in VLSI DRAM Cells”, 1986 IEEE International Electron Devices Meeting, Technical Digest, Los Angeles, CA,(Dec. 7-10, 1986),140-143.
Rayner Jr., G , et al., “The structure of plasma-deposited and annealed pseudo-binary ZrO2-SiO2 alloys”, Materials Research Society Symposium—Proceedings, 611, (2000),C131-C139.
Richardson, W. F., et al., “A Trench Transistor Cross-Point DRAM Cell”, IEEE International Electron Devices Meeting, Washington, D.C.,(Dec. 1-4, 1985),714-717.
Ritala, M. , “Atomic layer deposition of oxide thin films with metal alkoxides as oxygen sources”, Science, 288(5464), (Apr. 14, 2000),319-321.
Ritala, Mikko , “Atomic Layer Epitaxy Growth of Titanium, Zirconium and Hafnium Dioxide Thin Films”, Annales Academiae Scientiarum Fennicae, (1994),24-25.
Ritala, Mikko , “Zirconium dioxide thin films deposited by ALE using zirconium tetrachloride as precursor”, Applied Surface Science, 75, (Jan. 1994),333-340.
Robertson, J. , “Band offsets of wide-band-gap oxides and implications for future electronic devices”, Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 18(3), (May-Jun. 2000),1785-1791.
Rossnagel, S. M., et al., “Plasma-enhanced atomic layer deposition of Ta and Ti for Interconnect diffusion barriers”, Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 18(4), (Jul. 2000),2016-2020.
Rotondaro, A L., et al., “Advanced CMOS Transistors with a Novel HfSiON Gate Dielectric”, Symposium on VLSI Technology Digest of Technical Papers, (2002),148-149.
Ryu, Changsup , “Barriers for Copper Interconnections”, Solid State Technology, 42(4), (Apr. 1999),pp. 1-3.
Sagara, K. , “A 0.72 micro-meter2 Recessed STC (RSTC) Technology for 256Mbit DRAMs using Quarter-Micron Phase-Shift Lithography”, 1992 Symposium on VLSI Technology, Digest of Technical Papers, Seattle, WA,(Jun. 2-4, 1992),10-11.
Saito, Yuji , et al., “Advantage of Radical Oxidation for Improving Reliability of Ultra-Thin Gate Oxide”, 2000 Symposium on VLSI Technology Digest of Technical Papers, (2000),176-177.
Saito, Yuji, et al., “High-Integrity Silicon Oxide Grown at Low-Temperature by Atomic Oxygen Generated in High-Density Krypton Plasma”, Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, (1999),152-153.
Seevinck, E. , et al., “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's”, IEEE Journal of Solid State Circuits, 26(4), (Apr. 1991),pp. 525-536.
Senthinathan, R. , et al., “Reference Plane Parasitics Modeling and Their Contribution to the Power and Ground Path “Effective” Inductance as Seen by the Output Drivers”, IEEE Transactions on Microwave Theory and Techniques, 42, (Sep. 1994),1765-1773.
Shah, A. H., et al., “A 4-Mbit DRAM with Trench-Transistor Cell”, IEEE Journal of Solid-State Circuits, SC-21, (Oct. 1986),618-625.
Shah, A. H., et al., “A 4Mb DRAM with Cross-Point Trench Transistor Cell”, 1986 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, (Feb. 21, 1986),268-269.
Shanware, A , et al., “Reliability evaluation of HfSiON gate dielectric film with 12.8 A SiO2 equivalent thickness”, International Electron Devices Meeting. Technical Digest, (2001),6.6.1-6.6.4.
Sherony, M. J., “Reduction of Threshold Voltage Sensitivity in SOI MOSFET's”, IEEE Electron Device Letters, 16, (Mar. 1995),100-102.
Shimbo, M. , et al., “Silicon-to-Silicon direct bonding method”, J. Appl. Phys. vol. 60, No. 8, (Oct. 1986),2987-2989.
Shimizu, Takashi , et al., “Electrical Properties of Ruthenium/Metalorganic Chemical Vapor Deposited La-Oxide/Si Field Effect Transistors”, Jpn. J. Appl. Phys., vol. 42, Part 2, No. 11A, (2003),L1315-L1317.
Shimomura, K. , et al., “A 1V 46ns 16Mb SOI-DRAM with Body Control Technique”, 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, (Feb. 6, 1997),68-69.
Shin, Chang H., et al., “Fabrication and Characterization of MFISFET using AI2O3 Insulating Layer for Non-Volatile Memory”, 12th International Symposium in Integrated Ferroelectrics, (Mar. 2000),1-9.
Smith, Ryan C., “Chemical Vapour Deposition of the Oxides of Titanium, Zirconium and Hafnium for Use as High-k Materials in Microelectronic Devices. A Carbon-free Precursor for the Synthesis of Hafnium Dioxide”, Advanced Materials for Optics and Electronics, 10(3-5), (2000),105-114.
Sneh, Ofer , “Thin film atomic layer deposition equipment for semiconductor processing”, Thin Solid Films, 402(1-2), (2002),248-261.
Song, Hyun-Jung , et al., “Atomic Layer Deposition of Ta2O5 Films Using Ta(OC2H5)5 and NH3”, Ultrathin SiO2 and High-K Materials for ULSI Gate Dielectrics. Symposium, (1999),469-471.
Souche, D , et al., “Visible and infrared ellipsometry study of ion assisted SiO2 films”, Thin Solid Films, 313-314, (1998),676-681.
Stanisic, B. R., et al., “Addressing Noise Decoupling in Mixed-Signal IC's: Power Distribution Design and Cell Customization”, IEEE Journal of Solid-State Circuits, 30, (Mar. 1995),321-326.
Stathis, J. H., et al., “Reliability Projection for Ultra-Thin Oxides at Low Voltage”, Tech. Dig. International Electron Device Meeting, (1998),167-9
Stellwag, T. B., “A Vertically-Integrated GaAs Bipolar DRAM Cell”, IEEE Transactions on Electron Devices, 38, (Dec. 1991),2704-2705.
Su, D. K., et al., “Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits”, IEEE Journal of Solid-State Circuits, 28(4), (Apr. 1993),420-430.
Suma, Katsuhiro , et al., “An SOI-DRAM with Wide Operating Voltage Range by CMOS/SIMOX Technology”, IEEE Journal of Solid-State Circuits, 29(11), (Nov. 1994),pp. 1323-1329.
Summonte, C. , et al., “Wide band-gap silicon-carbon alloys deposited by very high frequency plasma enhanced chemical vapor deposition”, Journal of Applied Physics, 96 (7), (Oct. 1, 2004),3987-3997.
Sunouchi, K. , et al., “A Surrounding Gate Transistor (SGT) Cell for 64/256Mbit DRAMs”, 1989 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C.,(Dec. 3-6, 1989),23-26.
Sunouchi, K. , et al., “Process Integration for 64M DRAM Using an Asymmetrical Stacked Trench Capacitor (AST) Cell”, 1990 IEEE International Electron Devices Meeting, San Francisco, CA,(Dec. 9-12, 1990),647-650.
Suntola, T. , “Atomic Layer Epitaxy”, Handbook of Crystal Growth, 3; Thin Films of Epitaxy, Part B: Growth Mechanics and Dynamics, Amsterdam,(1994),601-663.
Suntola, Tuomo, “Atomic layer epitaxy”, Thin Solid Films, 216(1), (Aug. 28, 1992),84-89.
Sze, S. M., In: Physics of Semiconductor Devices, Second Edition, John Wiley & Sons, New York,(1981),p. 42.
Sze, S M., “Physics of Semiconductor Devices”, New York : Wiley, (1981),431.
Sze, S M., “Physics of Semiconductor Devices”, New York : Wiley, (1981),473.
Takai, M. , et al., “Direct Measurement and Improvement of Local Soft Error Susceptibility in Dynamic Random Access Memories”, Nuclear Instruments & Methods in Physics Research, B-99, (Nov. 7-10, 1994),562-565.
Takoto, H. , et al., “High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs”, IEEE International Electron Devices Meeting, Technical Digest, (1988),222-225.
Takato, H. , et al., “Impact of Surrounding Gate Transistor (SGT) for Ultra-High Density LSI's”, IEEE Transactions on Electron Devices, 38, (Mar. 1991),573-578.
Takemoto, J. H., et al., “Microstrip Resonators and Filters Using High-TC Superconducting Thin Films on LaAIO3”, IEEE Transaction on Magnetics, 27(2), (Mar. 1991),2549-2552.
Tanabe, N. , et al., “A Ferroelectric Capacitor Over Bit-Line (F-COB) Cell for High Density Nonvolatile Ferroelectric Memories”, 1995 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan,(Jun. 6-8, 1995),123-124.
Tarre, A , et al., “Comparative study of low-temperature chloride atomic-layer chemical vapor deposition of TiO2 and SnO2”, Applied Surface Science, 175-176, (May 2001),111-116.
Tavel, B , et al., “High performance 40 nm nMOSFETs with HfO2 gate dielectric and polysilicon damascene gate”, Technical Digest of International Electron Devices Meetings 2002, (2002),429-432.
Temmler, D. , “Multilayer Vertical Stacked Capacitors (MVSTC) for 64 Mbit and 256 Mbit DRAMs”, 1991 Symposium on VLSI Technology, Digest of Technical Papers, (May 28-30, 1991),13-14.
Terauchi, M. , “A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMs”, 1993 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan,(1993),21-22.
Tewg, J.Y. , “Electrical and Physical Characterization of Zirconium-Doped Tantalum Oxide Films”, Electrochemical Society Proceedings, vol. 2002-28, (2002),75-81.
Tong, Q. Y., et al., “Hydrophobic Silicon Wafer Bonding”, Applied Physics Letter 64(5), (Jan. 31, 1994),625-627.
Tsui, P. G., et al., “A Versatile Half-Micron Complementary BiCMOS Technology for Microprocessor-Based Smart Power Applications”, IEEE Transactions on Electron Devices, 42, (Mar. 1995),564-570.
Tyczkowski, J. , et al., “Electronic band structure of insulating hydrogenated carbon-germanium films”, Journal of Applied Physics, 86(8), (Oct. 15, 1999),4412-4418.
Van Dover, R. B., “Amorphous Ianthanide-doped TiOx dielectric films”, Applied Physics Letters, 74(20), (May 17, 1999),3041-3043.
Van Dover, Robert B., et al., “Deposition of Uniform Zr-Sn-Ti-O films by ON-Axis Reactive Sputtering”, IEEE Electron Device Letters, 19(9), (Sep. 1998),329-331.
Van Dover, R. B., “Discovery of a useful thin-film dielectric using a composition-spread approach”, Nature, 392, (Mar. 12, 1998),162-164.
Verdonckt-Vandebroek, S. , et al., “High-Gain Lateral Bipolar Action in a MOSFET Structure”, IEEE Transactions on Electron Devices 38, (Nov. 1991),2487-2496.
Viirola, H , “Controlled growth of antimony-doped tin dioxide thin films by atomic layer epitaxy”, Thin Solid Films, 251, (Nov. 1994),127-135.
Viirola, H , et al., “Controlled growth of tin dioxide thin films by atomic layer epitaxy”, Thin Solid Films, 249(2), (Sep. 1994),144-149.
Visokay, M R., “Application of HfSiON as a gate dielectric material”, Applied Physics Letters, 80(17), (Apr. 2002),3183-3185.
Vittal, A. , et al., “Clock Skew Optimization for Ground Bounce Control”, 1996 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, San Jose, CA,(Nov. 10-14, 1996),395-399.
Wang, N. , “Digital MOS Integrated Circuits”, Digital MOS Integrated Circuits, Prentice Hall, Inc. , Englewood Cliffs, NJ,(1989),p. 328-333.
Wang, P. W., “Excellent Emission Characteristics of Tunneling Oxides Formed Using Ultrathin Silicon Films for Flash Memory Devices”, Japanese Journal of Applied Physics, 35, (Jun. 1996),3369-3373.
Watanabe, H. , et al., “A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs”, IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA,(Dec. 13-16, 1992),259-262.
Watanabe, S. , et al., “A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's”, IEEE Journal of Solid-State Circuits, 30, (Sep. 1995),960-971.
Watanabe, H. , “A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs”, 1993 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan,(1993),17-18.
Watanabe, H. , “An Advanced Fabrication Technology of Hemispherical Grained (HSG) Poly-Si for High Capacitance Storage Electrodes”, Extended Abstracts of the 1991 International Conference on Solid State Devices and Materials, Yokohama, Japan,(1991),478-480.
Watanabe, H. , “Device Application and Structure Observation for Hemispherical-Grained Si”, J. Appl. Phys., 71, (Apr. 1992),3538-3543.
Watanabe, H. , “Hemispherical Grained Silicon (HSG-Si) Formation on In-Situ Phosphorous Doped Amorphous-Si Using the Seeding Method”, Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials, Tsukuba, Japan,(1992),422-424.
Weldon, M. K., et al., “Physics and Chemistry of Silicon Wafer bonding Investigated by Infrared Absorption Spectroscopy”, Journal of Vacuum Sci. Technology, B 14(4), c1996 American Vacuum Society,(Jul./Aug. 1996),3095-3106.
Wilk, G D., et al., “Hafnium and zirconium silicates for advanced gate dielectrics”, Journal of Applied Physics, 87(1), (Jan. 2000),484-492.
Wilk, G. D., “High-K gate dielectrics: Current status and materials properties considerations”, Journal of Applied Physics, 89(10), (May 2001),5243-5275.
Wolf, Stanley, et al., “Future Trends in Sputter Deposition Processes”, In: Silicon Processing of the VLSI Era, vol. 1, Lattice Press,(1986),374-380.
Wolf, Stanley , et al., “Silicon Processing for the VLSI Era—vol. I: Process Technology”, Second Edition, Lattice Press, Sunset Beach, California,(2000), 443.
Wolfram, G , et al., “Existence range, structural and dielectric properties of ZrxTiySnzO4 ceramics (x+y=2)”, Materials Research Bulletin, 16(11), (Nov. 1981),1455-63.
Yamada, T. , et al., “A New Cell Structure with a Spread Source/Drain (SSD) MOSFET and a Cylindrical Capacitor for 64-Mb DRAM's”, IEEE Transactions on Electron Devices, 38, (Nov. 1991),2481-2486.
Yamada, Hirotoshi , et al., “MOCVD of High-Dielectric-Constant Lanthanum Oxide Thin Films”, Journal of The Electrochemical Society, 150(8), (Aug. 2003),G429-G435.
Yamada, T. , et al., “Spread Source/Drain (SSD) MOSFET Using Selective Silicon Growth for 64Mbit DRAMs”, 1989 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C.,(Dec. 3-6, 1989),35-38.
Yamaguchi, Takeshi , “Band Diagram and Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by Pulsed-laser-ablation Deposition”, Electron Devices Meeting, 2000. IEDM Technical Digest. International, (2000),19-22.
Yamaguchi, Takeshi , et al., “Study on Zr-Silicate Interfacial Layer of ZrO2-MIS Structure Fabricated by Pulsed Laser Ablation Deposition Method”, Solid State Devices and Materials, (2000),228-229.
Yamamoto, K. , “Effect of Hf metal predeposition on the properties of sputtered HfO2/Hf stacked gate dielectrics”, Applied Physics Letters, 81, (Sep. 9, 2002),2053-2055.
Yeh, Ching-Fa , et al., “The advanced improvement of PN mesa junction diode prepared by silicon-wafer direct bonding”, 1991 International Symposium on VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, (May 22-24, 1991),136-140.
Zhang, H. , “Atomic Layer Deposition of High Dielectric Constant Nanolaminates”, Journal of The Electrochemical Society, 148(4), (Apr. 2001),F63-F66.
Zhang, H , et al., “High permitivity thin film nanolaminates”, Journal of Applied Physics, 87(4), (Feb. 2000),1921-1924.
Zhong, Huicai , et al., “Electrical Properties of Ru and RuO2 Gate Electrodes for Si-PMOSFET with ZrO2 and Zr-Silicate Dielectrics”, Journal of Electronic Materials, 30(12), (Dec. 2001),1493-1498.
Zhu, W , et al., “HfO2 and HfAIO for CMOS: Thermal Stability and Current Transport”, IEEE International Electron Device Meeting 2001, (2001),463-466.
Zucker, O , et al., “Application of Oxygen Plasma Processing to Silicon Direct Bonding”, Sensors and Actuators A, 36, (1993),227-231.
U.S. Appl. No. 10/137,058, filed May 2, 2002, Atomic Layer Deposition and Conversion.
U.S. Appl. No. 10/789,042, filed Feb. 27, 2004, LaAlO3 Films.
U.S. Appl. No. 11/215,451, filed Aug. 29, 2005, Systems and Apparatus for Atomic-Layer Deposition.
U.S. Appl. No. 10/909,959, filed Aug. 2, 2004, Zirconium-Doped Tantalum Oxide Films.
U.S. Appl. No. 10/931,533, filed Aug. 31, 2004, Method of Forming Apparatus Having Oxide Films Formed Using Atomic Layer Deposition.
U.S. Appl. No. 10/930,167, filed Aug. 31, 2004, Atomic Layer Deposited Lanthanum Aluminum Oxide Dielectric Layer.
U.S. Appl. No. 10/929,272, filed Aug. 30, 2004, Atomic Layer Deposition and Conversion.
U.S. Appl. No. 10/931,341, filed Aug. 31, 2004, Zr-Sn-Ti-O Films.
U.S. Appl. No. 10/930,431, filed Aug. 31, 2004, HfAlO3 Films for Gate Dielectrics.
U.S. Appl. No. 10/931,365, filed Aug. 31, 2004, Electronic Devices Having Lanthanide Dielectrics.
U.S. Appl. No. 10/931,845, filed Aug. 31, 2004, Methods, Systems, and Apparatus for Uniform Chemical-Vapor Depositions.
U.S. Appl. No. 10/931,595, filed Aug. 31, 2004, Methods, Systems, and Apparatus for Uniform Chemical-Vapor Depositions.
U.S. Appl. No. 11/029,757, filed Jan. 5, 2005, Methods for Fabricating Hafnium Tantalum Oxide Dielectrics.
U.S. Appl. No. 11/055,380, filed Feb. 10, 2005, Atomic Layer Deposition of CeO2/Al2O3 Films as Gate Dielectrics.
U.S. Appl. No. 11/053,577, filed Feb. 8, 2005, Atomic Layer Deposition of Dy-Doped HFO2 Films as Gate Dielectrics.
U.S. Appl. No. 11/031,289, filed Jan. 7, 2005, Lanthanide Doped TiOx Dielectric Films by Plasma Oxidation.
U.S. Appl. No. 11/093,104, filed Mar. 29, 2005, Atomic Layer Deposited Titanium Silicon Oxide Films.
U.S. Appl. No. 11/117,121, filed Apr. 28, 2005, Atomic Layer Deposited Zirconium Silicon Oxide Films.
U.S. Appl. No. 11/117,125, filed Apr. 28, 2005, Atomic Layer Deposition of a Ruthenium Layer to a Lanthanide Oxide Dielectric Layer.
U.S. Appl. No. 11/216,542, filed Aug. 30, 2005, Graded Dielectric Layers.
U.S. Appl. No. 11/197,184, filed Aug. 4, 2005, Method for Making Conductive Nanoparticle Charge Storage Element.
U.S. Appl. No. 11/084,968, filed Mar. 21, 2005, Zr-Sn-Ti-O Films.
U.S. Appl. No. 11/140,643, filed May 27, 2005, Hafnium Titanium Oxide Films.
U.S. Appl. No. 11/152,759, filed Jun. 14, 2005, Iridium / Zirconium Oxide Structure.
U.S. Appl. No. 11/178,914, filed Jul. 11, 2005, Nanolaminates of Hafnium Oxide and Zirconium Oxide.
U.S. Appl. No. 11/189,075, filed Jul. 25, 2005, Magnesium Titanium Oxide Films.
U.S. Appl. No. 11/216,958, filed Aug. 31, 2005, Cobalt Titanium Oxide Dielectric Films.
U.S. Appl. No. 11/216,474, filed Aug. 31, 2005, Lanthanum Aluminum Oxynitride Dielectric Films.
U.S. Appl. No. 11/215,578, filed Aug. 29, 2005, Zirconium-Doped Gadolinium Oxide Films.
U.S. Appl. No. 11/215,412, filed Aug. 29, 2005, Ruthenium Gate for a Lanthanide Oxide Dielectric Layer.
U.S. Appl. No. 11/213,013, filed Aug. 26, 2005, Electronic Apparatus With Deposited Dielectric Layers.
U.S. Appl. No. 11/459,792, filed Jul. 25, 2006, ZrAlxOy Dielectric Layers.
U.S. Appl. No. 11/212,306, filed Aug. 26, 2005, Atomic Layer Deposited Zirconium Titanium Oxide Films.
U.S. Appl. No. 11/214,693, filed Aug. 29, 2005, Atomic Layer Deposited Zr-Sn-Ti-O Films Using TiI4.
U.S. Appl. No. 11/297,567, filed Dec. 8, 2005, Lanthanide Yttrium Aluminum Oxide Dielectric Films.
U.S. Appl. No. 11/297,741, filed Dec. 8, 2005, Hafnium Tantalum Titanium Oxide Films.
U.S. Appl. No. 11/329,025, filed Jan. 10, 2006, Gallium Lanthanide Oxide Films.
U.S. Appl. No. 11/427,569, filed Jun. 29, 2006, Lanthanide Doped TiOX Dielectric Films.
U.S. Appl. No. 11/493,074, filed Jul. 26, 2006, Lanthanide Oxide / Hafnium Oxide Dielectric Layers.
U.S. Appl. No. 11/493,112, filed Jul. 26, 2006, Zirconium-Doped Tantalum Oxide Films.
U.S. Appl. No. 11/457,978, filed Jul. 17, 2006, Atomic Layer Deposited Nanolaminates of HfO2/ZrO2 Films as Gate Dielectrics.
U.S. Appl. No. 11/457,987, filed Jul. 17, 2006, Atomic Layer Deposited Nanolaminates of HfO2/ZrO2 Films as Gate Dielectrics.
U.S. Appl. No. 11/584,229, filed Oct. 20, 2006, Lanthanum Hafnium Oxide Dielectrics.
U.S. Appl. No. 11/528,776, filed Sep. 28, 2006, Atomic Layer Deposition of CeO2/Al2O3 Films as Gate Dielectrics.
U.S. Appl. No. 11/598,437, filed Nov. 13, 2006, Atomic Layer Deposited Zirconium Aluminum Oxide.
U.S. Appl. No. 11/566,038, filed Dec. 1, 2006, Lanthanum Aluminum Oxynitride Dielectric Films.
U.S. Appl. No. 11/608,281, filed Dec. 8, 2006, Zirconium-Doped Tantalum Oxide Films.
U.S. Appl. No. 11/565,826, filed Dec. 1, 2006, Hafnium Titanium Oxide Films.
U.S. Appl. No. 11/566,042, filed Dec. 1, 2006, Titanium Aluminum Oxide Films.
U.S. Appl. No. 11/608,286, filed Dec. 8, 2006, Lanthanum Aluminum Oxide Dielectric Layer.
U.S. Appl. No. 11/621,401, filed Jan. 9, 2007, Systems With a Gate Dielectric Having Multiple Lanthanide Oxide Layers.
U.S. Appl. No. 11/651,136, filed Jan. 9, 2007, Methods, Systems, and Apparatus for Uniform Chemical-Vapor Depositions.
U.S. Appl. No. 11/651,295, filed Jan. 9, 2007, Methods, Systems, and Apparatus for Uniform Chemical-Vapor Depositions.
U.S. Appl. No. 11/735,247, filed Apr. 13, 2007, Hafnium Tantalum Oxide Dielectrics.
U.S. Appl. No. 09/779,959, filed Feb. 9, 2001, External Matter.
U.S. Appl. No. 09/838,335, filed Apr. 20, 2001, External Matter.
U.S. Appl. No. 09/881,408, filed Jun. 13, 2001, External Matter.
U.S. Appl. No. 09/908,767, filed Jul. 18, 2001, External Matter.
Prior Publications
US 2007/0101929 A1 Methods for atomic-layer deposition 10-May-2007
Related Documents
Continuation of application No. US 10/137168 00, filed on 02-May-2002, now Pat. No. US 7160577 A.
Examiners
Primary: Turocy, David
Attorney, Agent or Firm
Schwegman, Lundberg & Woessner, P.A.

Supplemental Information (Source: DOCDB)
Inventors
AHN KIE Y [+1] [-1]
US
FORBES LEONARD
US
Assignees/Applicants
MICRON TECHNOLOGY INC
US
Priority
US 620324 A  05-Jan-2007 [+1] [-1]
US 137168 A  02-May-2002
Classifications
International (2010.01): C23C 16/00
International (2006.01): C23C 16/00; C23C 16/44; C23C 16/455
Preview up to the first 8 page images of this publication.
--- Page 1 ---
Page 1
--- Page 2 ---
Page 2
--- Page 3 ---
Page 3
--- Page 4 ---
Page 4
--- Page 5 ---
Page 5
--- Page 6 ---
Page 6
--- Page 7 ---
Page 7
--- Page 8 ---
Page 8
(Source: USPTO)
This application is a continuation of U.S. application Ser. No. 10/137,168 filed May 2, 2002, now U.S. Pat. No. 7,160,577, which is incorporated herein by reference.
TECHNICAL FIELD
This invention concerns methods of making integrated circuits, particularly layer formation techniques, such as chemical-vapor deposition and atomic-layer deposition.
BACKGROUND OF INVENTION
Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators generally build these circuits layer by layer, using techniques, such as deposition, doping, masking, and etching, to form and interconnect thousands and even millions of microscopic transistors, resistors, and other electrical components on a silicon substrate, known as a wafer.
One common technique for forming layers in an integrated circuit is called chemical vapor deposition. Chemical vapor deposition generally entails placing a substrate in a reaction chamber, heating the substrate to prescribed temperatures, and introducing one or more gases, known as precursor gases, into the chamber to begin a deposition cycle. The precursor gases enter the chamber through a gas-distribution fixture, such as a gas ring or a showerhead, one or more centimeters above the substrate, and descend toward the heated substrate. The gases react with each other and/or the heated substrate, blanketing its surface with a layer of material. An exhaust system then pumps gaseous by-products or leftovers from the reaction out of the chamber through a separate outlet to complete the deposition cycle.
Conventional chemical-vapor-deposition (CVD) systems suffer from at least two problems. First, conventional CVD systems generally form non-uniformly thick layers that include microscopic hills and valleys, and thus generally require use of post-deposition planarization or other compensation techniques. Second, it is difficult, if not impossible, for CVD to provide uniform coverage of trench sidewalls or complete filling of holes and trenches.
To address these shortcomings, fabricators have developed atomic-layer deposition (ALD), a special form of CVD that allows highly uniform formation of ultra-thin layers having thicknesses of one molecule or several atoms of the deposited material. Though similar to CVD in terms of equipment and process flow, ALD relies on adsorption of some of the reactants into exposed surfaces, and thus provides coverage and fill of structural features that are difficult, if not impossible, using CVD.
In recent years, researchers and engineers have made strides toward making ALD commercially viable for some applications. For example, one team of researchers reportedly optimized an ALD process for depositing an aluminum oxide (AlOx) film in thin-film heads—devices used to read and write magnetic data. See, Paranjpe et al., Atomic Layer Deposition of AlOx for Thin Film Head Gap Applications, Journal of Electrochemical Society, 148 (9), pp. G465-G471 (2001), which is incorporated herein by reference.
However, the present inventors have recognized that the equipment and processes reported as optimal for thin-film head applications suffer from some limitations relative to use in fabricating integrated circuits. For example, the reported process deposits material at the slow rate of less than one Angstrom per cycle, suggesting that more than 50 cycles would be necessary to form a 50-Angstrom-thick layer. Moreover, the reported equipment uses a larger than desirable reaction chamber, which takes longer to fill up or pump out, and thus prolongs the duration of each deposition cycle.
Accordingly, there is a need for better systems and methods of atomic-layer deposition of aluminum oxides as well as other material compositions.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a side view of an exemplary deposition reactor according to the invention;
FIG. 2 is a plan view of an exemplary gas-distribution fixture according to the invention; and
FIG. 3 is a flowchart showing an exemplary method according to the invention.
DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
The following detailed description, which references and incorporates the above-identified figures, describes and illustrates one or more specific embodiments of the invention. These embodiments, offered not to limit but only to exemplify and teach the invention, are shown and described in sufficient detail to enable those skilled in the art to make and use the invention. Thus, where appropriate to avoid obscuring the invention, the description may omit certain information known to those of skill in the art.
One exemplary atomic-layer deposition system, well suited for aluminum-oxide depositions in integrated-circuit fabrication, includes an outer chamber, a substrate holder, and a unique gas-distribution fixture. The fixture includes a gas-distribution surface having two sets of holes and a gas-confinement member that forms a wall around the holes. In operation, one set of holes dispenses an aluminum-carrying precursor and the other dispensing an oxidizing agent gas, after the gas-confinement member engages, or otherwise cooperates with the substrate holder to form an inner chamber within the outer chamber.
The inner chamber has a smaller volume than the outer chamber and thus consumes less gas during the deposition process than would the outer chamber used alone. Also, the smaller chamber volume allows the exhaust system to pump the chamber more quickly, thus allowing shorter ALD cycles and potentially increasing rates of production.
FIG. 1 shows an exemplary atomic-layer-deposition system 100 which incorporates teachings of the present invention. In particular, system 100 includes a chamber 110, a wafer holder 120, a gas-distribution fixture (or showerhead) 130, a gas-supply system 140, and exhaust pumps 150 and 160.
More particularly, chamber 110 includes respective top and bottom plates 112 and 114 and a sidewall 116. In the exemplary embodiment, chamber 110 is a cylindrical structure formed of stainless steel or glass. However, other embodiments use different structures and materials. Bottom plate 114 includes an opening 114A. Extending through opening 114A is a stem portion 122 of wafer holder 120.
Wafer holder 120 also includes a support platform 124, one or more heating elements 126, one or more temperature sensors 128, and an RF source 129. Holder 120 (also called a chuck) raises and rotates manually or automatically via lift and rotation devices, and is coupled to a power supply and temperature control circuitry (all of which are not shown). Support platform 124 supports one or more substrates, wafers, or integrated-circuit assemblies 200. Substrate 200 has an exemplary width or diameter of about 30 centimeters and an exemplary thickness in the range of 850-1000 microns. (The term “substrate,” as used herein, encompasses a semiconductor wafer as well as structures having one or more insulative, conductive, or semiconductive layers and materials. Thus, for example, the term embraces silicon-on-insulator, silicon-on-sapphire, and other advanced structures.)
Heating elements 126 and temperature sensors 128 are used for heating substrates 200 to a desired temperature. Radio Frequency (RF) source 129, for example, a 1.25-kilowatt-13.56-megahertz RF generator, is used to generate and sustain a capacitively coupled plasma between the wafer holder and gas-distribution fixture 130. (Some embodiments use generators with smaller or larger capacities.)
Fixture 130, positioned above wafer holder 120 and substrate 200, includes a gas-distribution member 132, a surface-projection (or gas-confinement) member 134, and gas inlets 136 and 137. In the exemplary embodiment, fixture 130 has three operating positions 138A, 138B, and 138C relative support platform 124. Fixture 130 takes operating position 138A, before and after depositions and operating position 138B during depositions. Position 138C is taken during a plasma anneal to ensure stability of the plasma.
Gas-distribution member 132 includes main gas inputs 132A and 132B, gas-distribution channels 132D and 132F, and gas-distribution holes 132E and 132G. Main gas inputs 132A and 132B feed respective gas-distribution channels 132D and 132F, which in turn feed respective gas-distribution holes 132E and 132G. (Holes 132E and 132G are actually interleaved in the exemplary embodiment, though shown simply in the figure as spatially segregated groups.) Holes 132D and 132F define a gas-distribution surface 132C.
In the exemplary embodiment, holes 132D and 132F are substantially circular with a common diameter in the range of 15-20 microns; gas-distribution channels 132D and 132F have a common width in the range of 20-45 microns; and surface 132C is substantially planar and parallel to platform 124 of wafer holder 120. However, other embodiments use other surface forms as well as shapes and sizes of holes and channels.
Extending from gas-distribution surface 132C is surface-projection member (or collar) 134. Member 134 projects or extends from surface 132C toward support platform 124, defining a fixture cavity 134A. The exemplary embodiment forms surface-projection member 134 from stainless steel as a uniform annular or circular wall or collar that projects perpendicularly from surface 132C to define a right-cylindrical cavity.
However, other embodiments form member 134 to project at other angles relative surface 132C. For example, some form the projection at an acute or obtuse angle, such as 45 or 135 degrees, and others form the projection to peripherally define an oval, ellipse, triangle, square, or any desirable regular or irregular polygon. Thus, the present invention encompasses a wide variety of projection shapes and configurations, indeed any projection shape that facilitates definition of an effective cavity or gas-confinement volume in cooperation with wafer holder 120 and/or substrate 200.
FIG. 2, a plan view, shows further details of the exemplary embodiment of gas-distribution fixture 130. In particular, the plan view shows not only exemplary circular peripheries of gas-distribution member 132 and surface-projection member 134, but also an exemplary interleaved distribution pattern for holes 132E and 132G, and an exemplary orthogonal arrangement of gas-distribution channels 132D and 132F. (Holes 132E are shown darkly shaded to distinguish them from holes 132G, which are cross-hatched.)
Other embodiments use other hole distribution patterns and channel arrangements. For example, some embodiments include random or concentric hole patterns and various channel geometries, including concentric circles, rectangles, or other regular or irregular concentric polygons. Some embodiments may also dedicate various subsets of channels and corresponding holes to different gases. For example, one embodiment provides one set of holes and channels for approximately uniform distribution of a gas or vapor, such as TMA precursor and argon carrier gas mixture, and another set of holes and channels for approximately uniform distribution of a gas or vapor, such as a water-argon mixture.
Gas-distribution member 132 can be made in a number of ways. One exemplary method entails laminating several material layers, with each layer including holes and/or channels to effect distribution of the gases to the separate holes. If the layers are made of silicon, the material layers can be patterned and etched, for example, using conventional photolithographic or micro-electro-mechanical systems (MEMS) technology, to form holes and channels. Dry-etching techniques produce small openings and channels, while wet etching produces larger openings and channels. For further details, see, for example, M. Engelhardt, “Modern Application of Plasma Etching and Patterning in Silicon Process Technology,” Contrib. Plasma Physics, vol. 39, no. 5, pp. 473-478 (1999). Also see co-pending and co-assigned U.S. patent application Ser. No. 09/797,324, which was filed on Mar. 1, 2001, now U.S. Pat. No. 6,852,167, and which is incorporated herein by reference.
The processed layers can then be bonded together with the holes and channels in appropriate alignment using known wafer-bonding techniques. See, for example, G. Krauter et al., “Room Temperature Silicon Wafer Bonding with Ultra-Thin Polymer Films,” Advanced Materials, vol. 9, no. 5, pp. 417-420 (1997); C. E. Hunt et al., “Direct Bonding of Micromachined Silicon Wafers for Laser Diode Heat Exchanger Applications,” Journal of Micromechan. Microeng, vol. 1, pp. 152-156 (1991); Zucker, O. et al., “Applications of oxygen plasma processing to silicon direct bonding,” Sensors and Actuators, A. Physical, vol. 36, no. 3, pp. 227-231 (1993), which are all incorporated herein by reference. See also, co-pending and co-assigned U.S. patent application Ser. No. 09/189,276 entitled “Low Temperature Silicon Wafer Bond Process with Bulk Material Bond Strength,” which was filed Nov. 10, 1998, now U.S. Pat. No. 6,423,613, and which is also incorporated herein by reference. The resulting bonded structure is then passivated using thermal oxidation for example.
For an alternative fixture structure and manufacturing method that can be combined with those of the exemplary embodiment, see U.S. Pat. No. 5,595,606, entitled “Shower Head and Film Forming Apparatus Using Same, which is incorporated herein by reference. In particular, one embodiment based on this patent adds a projection or gas-confinement member to the reported showerhead structure.
FIG. 1 also shows that gas inlets 136 and 137, which feed respective holes 132E and 132G, are coupled to gas-supply system 140. Specifically, gas-supply system 140 includes gas lines 142 and 143, gas sources 144, 145, and 146, and manual or automated mass-flow controllers 147, 148, and 149. Gas line or conduit 142, which includes one or more flexible portions (not specifically shown), passes through an opening 116A in chamber sidewall 116 to connect with gas inlet 136. Gas sources 144 and 145 are coupled respectively via mass-flow controllers 147 and 148 to gas line 142. Gas line 143, which also includes one or more flexible portions (not specifically shown), passes through an opening 116B in chamber sidewall 116 is coupled via mass-flow controller 149 to source 146.
In the exemplary embodiment, which is tailored for aluminum oxide deposition, source 144 provides a vapor-drawn aluminum precursor, such as trimethylaluminum (TMA) with a vapor pressure of 11 Torr at room temperature; source 145 provides a carrier gas, such as argon; and source 146 provides an oxidant, such as a water-argon mixture. The water-argon mixture can be implemented by bubbling an argon carrier through a water reservoir. Other embodiments use other aluminum precursors, such as triisobutylaluminum (TIBA), dimethylaluminum hydride (DMAH), AlC3, and other halogenated precursors and organometallic precursors. Other types of oxidants include H2O2, O2, O3, N2O. Thus, the present invention is not limited to specific aluminum precursors or oxidants.
System 100 also includes vacuum pumps 150 and 160. Vacuum pump 150 is coupled to gas-distribution fixture 130 via a mass-flow controller 152 and gas line 142. And, vacuum pump 160 is coupled to the interior of chamber 110 via a line 162 and an opening 114B in chamber bottom plate 114.
In general operation, system 100 functions, via manual or automatic control, to move gas-distribution fixture 130 from operating position 138A to position 138B, to introduce reactant gases from sources 145, 146, and 147 through holes 132E and 132G in gas-distribution fixture 130 onto substrate 200, and to deposit desired matter, such as an aluminum oxide, onto a substrate.
More particularly, FIG. 3 shows a flowchart 300 which illustrates an exemplary method of operating system 100. Flowchart 300 includes process blocks 302-320.
The exemplary method begins at block 302 with insertion of substrate 200 onto wafer holder 120. Execution then proceeds to block 304.
In block 304, the system forms or closes an inner chamber around substrate 200, or at least a portion of substrate 200 targeted for deposition. In the exemplary embodiment, this entails using a lever or other actuation mechanism (not shown) to move gas-distribution fixture 130 from position 138A to position 138B or to move wafer holder 120 from position 138B to 138A. In either case, this movement places gas-distribution surface 132C 10-20 millimeters from an upper most surface of substrate 200. In this exemplary position, a lower-most surface of surface-projection member 134 contacts the upper surface of support platform 124, with the inner chamber bounded by gas-distribution surface 132C, surface-projection member 134, and the upper surface of support platform 124.
Other embodiments define the inner chamber in other ways. For example, some embodiments include a surface-projection member on support platform 124 of wafer holder 120 to define a cavity analogous in structure and/or function to cavity 134A. In these embodiments, the surface-projection member takes the form of a vertical or slanted or curved wall, that extends from support platform 124 and completely around substrate 200, and the gas-distribution fixture omits a surface-projection member. However, some embodiments include one or more surface-projection members on the gas-distribution fixture and the on the support platform, with the projection members on the fixture mating, engaging, or otherwise cooperating with those on the support platform to define a substantially or effectively closed chamber. In other words, the inner chamber need not be completely closed, but only sufficiently closed to facilitate a desired deposition.
In block 306, after forming the inner chamber, the exemplary method continues by establishing desired ambient conditions for the desired deposition. This entails setting temperature and pressure conditions within chamber 110, including cavity 134A. To this end, the exemplary embodiment operates heating element 126 to heat substrate 200 to a desired temperature, such as 150-200° C., and operating vacuum pump 150 and/or pump 160 to establish a desired ambient pressure, such as 3.0 Torr. Gas-distribution fixture 130 is held at a temperature 30-50° C. warmer than its surroundings. (However, other embodiments can maintain the fixture at other relative operating temperatures.) After establishing the desired ambient conditions, execution continues at block 308.
Block 308 entails hydroxylating the surface of substrate 200 by introducing an oxidant into the separate chamber. To this end, the exemplary embodiment shuts mass-flow controllers 147 and 148 and operates mass-flow controller 149 to transfer an oxidant, such as a water in an argon carrier, from source 146 through gas line 143 and holes 132G into cavity 134A for a period, such as two seconds.
Notably, the inner chamber is smaller in volume than chamber 100 and thus requires less gas and less fill time to achieve desired chemical concentrations (assuming all other factors equal.) More precisely, the exemplary embodiment provides an inner chamber with an empty volume in the range of 70 to 350 cubic centimeters, based on a 1-to-5 millimeter inner-chamber height and a fixture with a 30-centimeter diameter. Additionally, the number and arrangement of holes in the fixture as well as the placement of the holes close to the substrate, for example within five millimeters of the substrate, promote normal gas incidence and uniform distribution of gases over the targeted portion of substrate 200.
Block 310 entails purging or evacuating the inner chamber to reduce water concentration in the gas-distribution fixture and inner chamber to trace levels. To this end, the exemplary method initially drives a high flow of argon gas from source 145 through fixture 130 into the inner chamber and then draws the gas out of the inner chamber through the fixture via vacuum pump 150, defining a purge cycle of less than five seconds, for example three-four seconds. The present invention, however, is not believed to be limited to any particular purge-cycle duration.
Next, as block 312 shows, the exemplary method introduces an aluminum precursor into the inner chamber through gas-distribution fixture 130. This entail operating mass-flow controllers 147 and 148 to respectively allow the flow of TMA and an argon carrier into fixture 130 via line 142 for a period of time such as 0.5-2.0 seconds. During this period, the argon carries the TMA to the hydroxylated surface of the substrate, causing formation of an approximately 0.8 Angstrom (Å) monolayer of aluminum oxide (AlOx).
Block 314 entails purging or evacuating the inner chamber to reduce precursor concentration in the gas-distribution fixture and inner chamber to trace levels. To this end, the exemplary method initially drives a flow of argon gas from source 145 through fixture 130 into the inner chamber and then draws the gas out of the inner chamber through the fixture via vacuum pump 150. Again, this purge cycle is expected to consume less than five seconds.
At this point, as represented by a return path 315 back to block 304, blocks 304-314 can be repeated as many times as desired to achieve an aluminum-oxide layer within roughly one Angstrom of virtually any desired thickness from 5-10 Angstroms upwards. For semiconductor applications, such as forming gate dielectrics, thicknesses in the range of 50-80 Angstroms could be used.
Block 316 entails annealing the substrate and deposited aluminum-oxide layer to enhance the dielectric breakdown voltage of the layer. In the exemplary embodiment, this entails moving fixture 130 to operating position 138C (which establishes a substrate-to-fixture separation in the range of 30-50 millimeters) and using RF source 129 to generate a 250 Watt capacitively coupled plasma at 0.12 Torr in an argon-oxygen atmosphere (10 atom percent O2) between the wafer holder. Some embodiments anneal after every monolayer to maximize dielectric breakdown strength, and some anneal after each 25-50 Angstroms of deposited material thickness. Though various anneal times are feasible, the exemplary embodiment anneals for 10-15 seconds in high-temperature environment. A return path 317 back to block 304 indicates that blocks 304-316 can be repeated as many times as desired.
In block 318, the system opens the separate chamber. In the exemplary embodiment, this entails automatically or manually moving gas-distribution fixture 130 to position 138A. Other embodiments, however, move the wafer holder or both the fixture and the wafer holder. Still other embodiments may use multipart collar or gas-confinement members which are moved laterally relative the wafer holder or gas-distribution fixture to open and close an inner chamber.
In block 320, substrate 200 is unloaded from chamber 110. Some embodiments remove the substrate manually, and others remove it using an automated wafer transport system.
CONCLUSION
In furtherance of the art, the inventors have presented new systems, methods, and apparatuses for atomic-layer deposition. One exemplary system includes an outer chamber, a substrate holder, and a unique gas-distribution fixture. The fixture engages, or otherwise cooperates with the substrate holder to form an inner chamber within the outer chamber. Notably, the inner chamber not only consumes less gas during deposition to reduce deposition waste and cost, but also facilitates rapid filling and purging to reduce deposition cycle times (with all other factors being equal.)
The embodiments described above are intended only to illustrate and teach one or more ways of practicing or implementing the present invention, not to restrict its breadth or scope. The actual scope of the invention, which embraces all ways of practicing or implementing the invention, is defined only by the following claims and their equivalents.
(Source: USPTO)
The invention claimed is:
1. A method comprising: forming a material on a substrate by atomic-layer deposition including: substantially enclosing the substrate in an inner chamber prior to exposing the substrate to precursors to form the material, the inner chamber formed within a chamber of an atomic-layer deposition system; exposing the substrate to the precursors by sending the precursors through a gas-distribution fixture of the atomic-layer deposition system into the inner chamber; and after exposing the substrate to one or more of the precursors, evacuating one or more gases from the inner chamber exiting through an opening in the gas-distribution fixture through which at least one of the precursors is sent into the inner chamber.
2. The method of claim 1, wherein the method includes holding the gas-distribution fixture to a temperature warmer than its surroundings.
3. The method of claim 1, wherein exposing the substrate to the precursors includes exposing the substrate to an oxidant precursor and one or more of a halogenated precursor or an organometallic precursor.
4. The method of claim 1, wherein forming a material on a substrate by atomic-layer deposition includes forming an oxide by the atomic-layer deposition.
5. The method of claim 4, wherein forming an oxide by the atomic-layer deposition includes forming aluminum oxide by the atomic-layer deposition.
6. A method comprising: forming a material as a gate dielectric on a substrate by atomic-layer deposition including: substantially enclosing the substrate in an inner chamber prior to exposing the substrate to precursors to form the material, the inner chamber formed within a chamber of an atomic-layer deposition system; exposing the substrate to the precursors by sending the precursors through a gas-distribution fixture of the atomic-layer deposition system into the inner chamber; and after exposing the substrate to one or more of the precursors, evacuating one or more gases from the inner chamber exiting through an opening in the gas-distribution fixture through which at least one of the precursors is sent into the inner chamber.
7. The method of claim 6, wherein substantially enclosing the substrate in an inner chamber includes moving a wafer holder that holds the substrate during processing towards the gas-distribution fixture.
8. The method of claim 6, wherein exposing the substrate to the precursors by sending the precursors through a gas-distribution fixture includes distributing different precursors through separate holes in the gas-distribution fixture.
9. The method of claim 6, wherein forming a material as a gate dielectric includes forming aluminum oxide by atomic layer deposition.
10. A method comprising: forming a material as a gate dielectric on a substrate by atomic-layer deposition including: substantially enclosing the substrate in an inner chamber prior to exposing the substrate to precursors to form the material, the inner chamber formed within a chamber of an atomic-layer deposition system; exposing the substrate to the precursors by sending the precursors through a gas-distribution fixture of the atomic-layer deposition system into the inner chamber; and after exposing the substrate to one or more of the precursors, evacuating one or more gases from the inner chamber exiting through an opening in the gas-distribution fixture through which at least one of the precursors is sent into the inner chamber, wherein substantially enclosing the substrate in an inner chamber includes moving the gas-distribution fixture towards the substrate.
11. A method comprising: forming an oxide on a substrate by atomic-layer deposition including: substantially enclosing the substrate in an inner chamber prior to exposing the substrate to precursors to form the oxide, the inner chamber formed within a chamber of an atomic-layer deposition system; hydroxylating a surface of the substrate by exposing the surface to at least one of the precursors by sending the at least one of the precursors through a gas-distribution fixture of the atomic-layer deposition system into the inner chamber; exposing the hydroxylated surface to another of the precursors to form the oxide; and after exposing the surface to one or more of the precursors, evacuating one or more gases from the inner chamber exiting through an opening in the gas-distribution fixture to a gas supply line, the gas supply line configured to supply, to the inner chamber, a non-oxygen element to form the oxide containing the non-oxygen element.
12. The method of claim 10, wherein hydroxylating a surface of the substrate includes exposing the surface to an oxidant precursor.
13. The method of claim 11, wherein exposing the hydroxylated surface to another of the precursors includes exposing the hydroxylated surface to one or more of a halogenated precursor or an organometallic precursor.
14. The method of claim 11, wherein forming an oxide includes forming aluminum oxide.
15. The method of claim 11, wherein the method includes repeating hydroxylating a surface and exposing the hydroxylated surface substrate to form the oxide until the oxide has a specified thickness.
16. A method comprising: forming a material on a substrate by atomic-layer deposition including: substantially enclosing the substrate in an inner chamber prior to exposing the substrate to precursors to form the material, the inner chamber formed within a chamber of an atomic-layer deposition system; exposing the substrate to the precursors by sending the precursors through a gas-distribution fixture of the atomic-layer deposition system into the inner chamber; and after exposing the substrate to one or more of the precursors, evacuating one or more gases from the inner chamber exiting through an opening in the gas-distribution fixture through which at least one of the precursors is sent into the inner chamber; and annealing the material formed on the substrate.
17. method of claim 16, wherein the method includes at least partially opening the inner chamber after forming the material on the substrate and before annealing the material on the substrate.
18. The method of claim 17, wherein annealing the material on the substrate includes applying a plasma anneal.
19. The method of claim 18, wherein forming the material includes forming aluminum oxide and applying a plasma anneal includes using a RF source.
20. The method of claim 16, wherein the method includes annealing in an argon-oxygen atmosphere.
21. A method comprising: forming a dielectric material on a substrate by atomic-layer deposition including: substantially enclosing the substrate in an inner chamber prior to exposing the substrate to precursors to form the dielectric material, the inner chamber formed within a chamber of an atomic-layer deposition system; exposing the substrate to the precursors by sending the precursors through a gas-distribution fixture of the atomic-layer deposition system into the inner chamber; and after exposing the substrate to one or more of the precursors, evacuating one or more gases from the inner chamber exiting through an opening in the gas-distribution fixture through which at least one of the precursors is sent into the inner chamber; and annealing the dielectric material formed on the substrate.
22. The method of claim 21, wherein annealing the dielectric material on the substrate includes annealing after each 25-50 Angstroms of the dielectric material deposited prior to completely forming the layer of the dielectric material to a final thickness.
23. The method of claim 21, wherein annealing the dielectric material on the substrate includes annealing after every monolayer of the dielectric material formed by atomic-layer deposition.
24. The method of claim 21, wherein forming a dielectric material includes forming aluminum oxide.
25. The method of claim 21, wherein annealing the dielectric material on the substrate includes annealing after forming a layer of the dielectric material prior to completely forming the layer of the dielectric material to a final thickness.
(Source: USPTO)