Crossbar-memory systems and methods for writing to and reading from crossbar memory junctions of crossbar-memory systems (17-Aug-2010)

TECHNICAL FIELD

The present invention is related to nanoscale and combined microscale/nanoscale electronics and, in particular, to crossbar-memory systems configured so that information can be written to, and read from, crossbar memory junctions of the crossbar-memory systems.

BACKGROUND OF THE INVENTION

Significant research and development efforts are currently directed towards designing and manufacturing nanoscale electronic devices, including nanoscale memories. Nanoscale electronics promise a number of advantages over microscale, photolithography-based electronics, including significantly reduced features sizes and the potential for self-assembly and for other relatively inexpensive, non-photolithography-based fabrication methods. However, the design and manufacture of nanoscale electronic devices present many new problems that need to be addressed prior to large-scale commercial production of nanoscale electronic devices and incorporation of nanoscale electronic devices into microscale and larger-scale systems, devices, and products.

Nanoscale crossbar-memory arrays are possible candidates for relatively near-term commercialization. Nanoscale crossbar-memory arrays can be composed of a first layer of approximately parallel nanowires overlain by a second layer of approximately parallel nanowires, the orientation of the nanowires of the first layer are approximately perpendicular to the nanowires of the second layer. A resistor is located at each point where a nanowire in the second layer overlaps a nanowire in the first layer and is called a “crossbar-memory junction.” The nanowires of the first layer are addressed through selective interconnections to microscale output signal lines of a first combined microscale/nanoscale encoder-demultiplexer, and the nanowires of the second layer are addressed through selective interconnections to microscale output signal lines of a second combined microscale/nanoscale encoder-demultiplexer. Resistors are located at selected combined microscale/nanoscale crossbar junctions of the encoder-demultiplexers. A nanowire address is input to an encoder via microscale address lines and is transformed into a pattern of addressed-nanowire selection voltages that are output by the encoder to the microscale output signal lines of the encoder-demultiplexer. Selection of the two nanowires that cross at a particular crossbar-memory junction by the two encoder-demultiplexers results in applying a defined voltage to the crossbar-memory junction selected by input of two nanowire addresses to the two encoder-demultiplexers.

Relatively large voltages can be applied to a given crossbar-memory junction to reversibly configure the resistor in a high-conductance state or low-conductance state, the particular conductance state obtained depending on the polarity of the applied voltage. However, application of voltages greater in magnitude than the voltages used to reversibly configure crossbar-memory junctions can irreversibly destroy the crossbar-memory junctions to which the greater voltages are applied. Each crossbar-memory junction serves as a single-bit memory element, storing a binary value “0” as a low conductance state and a binary value “1” as a high-conductance state.

Although the encoder-demultiplexers and the crossbar memories are similar in that both are implemented using nanoscale crossbars that have configurable resistors at the crossbar junctions, there are important differences between the resistors used in the two subsystems. The resistors in the memory array are used as memory storage elements, and are therefore electronically-reconfigurable. By contrast, the resistors in the encoder-demultiplexers are configured once at the time of manufacturing, and are stable thereafter. However, designers, manufacturers, and users of nanoscale crossbar-memory arrays have recognized a need for crossbar memory arrays with electronically-reconfigurable crossbar resistors at crossbar memory junctions that provide large voltage margins, defect tolerant properties, and can be used with encoder-demultiplexers that use redundant addressing schemes based on error-correcting codes. In addition, designers, manufacturers, and users have recognized a need for methods of writing information to and reading information stored in crossbar memory junctions.

SUMMARY OF THE INVENTION

Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system comprises a first layer of microscale signal lines, a second layer of microscale signal lines, a first layer of one or more nanowires configured so that each first layer nanowire overlaps each first layer microscale signal line, and a second layer of one or more nanowires configured so that each second layer nanowire overlaps each second layer microscale signal line and overlaps each first layer nanowire. The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires to first layer microscale signal lines and to selectively connect second layer nanowires to second layer microscale signal lines. The crossbar-memory system also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire at each crossbar intersection.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a nanowire crossbar array.

FIGS. 2A-2B illustrate a crossbar junction that interconnects two overlapping nanowires of two contiguous layers within a nanowire crossbar.

FIGS. 3A-3D illustrate one possible approach to configuring a network of reconfigurable nanoscale electrical components from a two-layer nanowire crossbar.

FIG. 4 shows a current-versus-voltage curve that describes the operational characteristics of a nonlinear-tunneling-resistor junction.

FIG. 5 shows the operational characteristics of a nonlinear-tunneling-hysteretic-resistor junction and resistance-state transitions under operational control voltages.

FIG. 6A illustrates a number of parallel nonlinear-tunneling resistors, where each nonlinear tunneling resistor has an identical scale factor and quasi-conductance.

FIG. 6B illustrates a voltage divider composed of two nonlinear-tunneling resistors.

FIG. 7 shows a diagram of a combined nanoscale/microscale electronic memory device.

FIG. 8 shows an abstract representation of a nanowire-crossbar memory-element subarray within a combined nanoscale/microscale electronic memory device.

FIG. 9 illustrates a portion of a grid-like nanowire crossbar featuring nonlinear-tunneling-hysteretic-resistor junctions, as described above with reference to FIG. 5.

FIG. 10 illustrates a microscale/nanoscale crossbar and encoder of a microscale/nanoscale encoder-demultiplexer.

FIG. 11 shows a table representing a constant-weight error-control-encoding code.

FIGS. 12A-12B illustrate a distance profile and a distance distribution for an example 4-bit constant-weight code.

FIG. 13 illustrates an example crossbar-memory system configured to store and retrieve information that represents a first embodiment of the present invention.

FIG. 14 illustrates an example configuration of a crossbar-memory system that is structurally similar to the crossbar-memory system shown in FIG. 13 and represents a second embodiment of the present invention.

FIG. 15 illustrates an example crossbar-memory system that represents an embodiment of the present invention.

FIG. 16 illustrates an enlargement of a microscale/nanoscale encoder-demultiplexer shown in FIG. 15 that represents an embodiment of the present invention.

FIGS. 17A-17B illustrate an example of a voltage-divider representation of a nanowire of the encoder-demultiplexer shown in FIG. 16 that represents an embodiment of the present invention.

FIGS. 18A-18B show a general voltage-divider representation of a nanowire interconnected to a number of microscale signal lines of an encoder demultiplexer that represents an embodiments of the present invention.

FIGS. 19A-19D show voltage outputs from nanowires of an encoder demultiplexer employing tunneling-resistor junctions that represents one of many embodiments of the present invention.

FIG. 20 illustrates applying a write voltage to a selected crossbar memory junction of the crossbar-memory system shown in FIG. 13 that represents an embodiment of the present invention.

FIG. 21 illustrates writing a memory state to a selected crossbar memory junction of the crossbar-memory array shown in FIG. 15 that represents an embodiment of the present invention.

FIG. 22 shows voltage drops across each crossbar memory junction of the crossbar-memory array shown in FIG. 15 that represents an embodiment of the present invention.

FIG. 23 shows an ideal conductance path that passes through a selected crossbar memory junction of the crossbar-memory system shown in FIG. 13 that represents an embodiment of the present invention.

FIGS. 24A-24B illustrates changing a conductance state of crossbar memory junctions in the crossbar-memory system shown in FIG. 13 that represents an embodiment of the present invention.

FIG. 25 illustrates current flowing along an ideal conductance path in the crossbar-memory system shown in FIG. 13 that represents an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Various embodiments of the present invention are directed to crossbar-memory systems and methods for writing information to, and reading information from, the crossbar-memory systems. The crossbar-memory systems comprise a crossbar-memory array with electronically reconfigurable nonlinear-tunneling resistors located at crossbar memory junctions of the crossbar-memory array, switch multiplexers, and two combined microscale/nanoscale demultiplexers that include nonlinear-tunneling resistors located at selected microscale signal line and nanowire junctions. The two combined microscale/nanoscale demultiplexers are designed to use redundant addressing schemes based on error-correcting codes. In order to assist in understanding descriptions of various embodiments of the present invention, an overview of crossbar arrays and crossbar junctions in provided in a first subsection. An overview of properties of nonlinear-tunneling resistors located at crossbar junctions is provided in a second subsection. An overview of nanoscale crossbar-memory arrays is provided in a third subsection. A mathematical description of error-correcting codes is provided in a fourth subsection. Finally, various device embodiments and various writing and reading method embodiments are described in a fifth subsection.

Crossbar Arrays and Crossbar Junctions

FIG. 1 illustrates a nanowire crossbar array. In FIG. 1, a first layer of approximately parallel nanowires 102 is overlain by a second layer of approximately parallel nanowires 104. The second layer 104 is roughly perpendicular, in orientation, to the nanowires of the first layer 102, although the orientation angle between the layers may vary. The two layers of nanowires form a lattice, or crossbar, each nanowire of the second layer 104 overlying all of the nanowires of the first layer 102 and coming into close contact with each nanowire of the first layer 102 at nanowire intersections that represent the closest contact between two nanowires. Although individual nanowires in FIG. 1 are shown with rectangular cross sections, nanowires can also have square, circular, elliptical, or more complex cross sections. The nanowires may also have many different widths or diameters and aspect ratios or eccentricities. The term “nanowire crossbar” may refer to crossbars having one or more layers of sub-microscale wires, microscale wires, or wires with larger dimensions, in addition to nanowires.

Nanowire layers can be fabricated by mechanical nanoimprinting techniques. Alternatively, nanowires can be chemically synthesized and can be deposited as layers of approximately parallel nanowires in one or more process steps, including Langmuir-Blodgett processes. Other alternative techniques for fabricating nanowires may also be employed. Thus, a two-layer nanowire crossbar comprising first and second layers, as shown in FIG. 1, can be manufactured by any of numerous relatively straightforward processes. Many different types of conductive and semi-conductive nanowires can be chemically synthesized from metallic and semiconductor substances, from combinations of these types of substances, and from other types of substances. A nanowire crossbar may be connected to microscale address-wire leads or other electronic leads, through a variety of different methods in order to incorporate the nanowires into electrical circuits.

At nanowire intersections, nanoscale electronic components, such as resistors, and other familiar basic electronic components, can be fabricated to interconnect two overlapping nanowires. A nanowire intersection connected by electronic components is called a “crossbar junction.” FIGS. 2A-2B provide two different illustrations of a crossbar junction that interconnects nanowires 202 and 204 of two contiguous layers within a nanowire crossbar. The crossbar junction may or may not involve physical contact between the two nanowires 202 and 204. As shown in FIG. 2A, the two nanowires are not in physical contact at their overlap point, but the gap between the nanowires 202 and 204 is spanned by a number of molecules represented by a resistive element 206 that lies between the two nanowires at their closest overlap point. FIG. 2B illustrates a schematic representation of the resistive element 206 and overlapping nanowires 202 and 204 shown in FIG. 2A. The resistive element 206 is used to represent a resistor located at a crossbar junction throughout the remaining figures. The resistive element 206 may represent one or more molecules that behave as a resistor. In certain embodiments of the present invention, the resistive element 206 may be introduced in a separate layer, referred to as “intermediate layer,” formed between the layers of overlapping nanowires and configured, as described below with reference to FIGS. 3A-3D.

The electronic properties of crossbar-junction molecules can vary according to the particular molecular configuration or electronic state of the crossbar-junction molecules. In some cases, changes in the state of crossbar-junction molecules may not be reversible. In other cases, the crossbar-junction molecules may be conductive, but the molecules may be irreversibly damaged, along with portions of the nanowires proximal to the crossbar junctions, through application of very high voltages, resulting in disrupting conductivity between the two nanowires and breaking of an electrical connection between them. In yet other cases, the crossbar-junction molecules may transition reversibly from one state to another and back, so that the resistive elements configured at crossbar junctions may be reconfigured, or programmed, by application of differential voltages to selected crossbar junctions.

Various different types of molecules may be introduced at crossbar junctions for a variety of different purposes, such as to control the level of current passing between two overlapping nanowires. The molecules spanning a crossbar junction, as shown in FIG. 2A, may have various different states in which the molecules exhibit resistive, semiconductor-like, or conductive electrical properties. The states, and relative energies of the states, of the crossbar-junction molecules may be controlled by applying differential current levels or voltages to the overlapping nanowires forming the crossbar junction. For example, certain states of a crossbar-junction molecule can be set by applying voltages to nanowires of a crossbar junction. The applied voltages can change the redox state of the crossbar-junction molecule causing the crossbar-junction molecule to operate as a conductor in a reduced state or operate as an insulator in an oxidized state.

Crossbar junctions can be configured electrically, optically, mechanically or by other means. FIGS. 3A-3D illustrate one possible approach to configuring a network of reconfigurable nanoscale electrical components from a two-layer nanowire crossbar. The example shown in FIGS. 3A-3D are meant to illustrate a general process by which nanowire crossbars may be configured as useful portions of electronic circuits. In FIGS. 3A-3D, a small 3×3 nanowire crossbar is shown, with circles at all nine crossbar junctions, each circle indicating the state of the crossbar-junction molecules. In one state, labeled “1” in FIGS. 3A-3D, the crossbar-junction molecules may have resistive properties, while in a second state, labeled “2” in FIGS. 3A-3D, the crossbar-junction molecules may have different properties that cause the crossbar-junction molecules to operate as insulators. Initially, as shown in FIG. 3A, the states of the crossbar junctions of the nanowire crossbar 300 are labeled “2.” Next, as shown in FIG. 3B, each crossbar junction may be uniquely accessed by applying a WRITE voltage, or configuring voltage, to the nanowires that form the crossbar junction in order to configure, or program, the crossbar junction to have the state “1.” For example, in FIG. 3B, a first WRITE voltage v_w′ is applied to horizontal nanowire 302 and a second WRITE voltage v_w″ is applied to vertical nanowire 304 to change the state of the crossbar junction 306 from “2” to “1.” Individual crossbar junctions may be configured through steps similar to the steps shown in FIG. 3B, resulting in a fully configured nanoscale component network as shown in FIG. 3C. In FIG. 3C, the states of crossbar junctions 306, 308, and 310 form a downward-slanted diagonal through the nanowire crossbar that have been configured by selective application of WRITE voltages. As shown in FIG. 3D, the nanoscale electrical component network can be used as a portion of an integrated circuit. Input voltages v_i′, v_i″, and v_i′″ may be applied to the nanoscale electrical component lattice as inputs 312 and output voltages v_o′, v_o″, and v_o′″ 314 may be accessed as the result of operation of the nanoscale electrical component network that represents a portion of an integrated circuit. In general, the input voltages v_i′, v_i″, and v_i′″ and the output voltages v_o′, v_o″, and v_o′″ have relatively low magnitudes compared with the WRITE voltages v_w. Depending on the types of nanowires, types of dopants employed in the case of semiconductor nanowires, and the types of crossbar-junction molecules employed in the nanowire crossbar, many different configuring processes may be used to configure nanowire crossbars into nanowire-based electrical components networks.

Properties of Nonlinear-Tunneling Resistors at Crossbar Junctions

A current flowing between two overlapping nanowires interconnected by crossbar-junction molecules that operate as a nonlinear tunneling resistor can be modeled by the current-voltage equation:

I = 1 2 ⁢ ( k ⁢ ⁢ ⅇ aV - k ⁢ ⁢ ⅇ - aV ) = k ⁢ ⁢ sinh ⁡ ( aV )
where I is current flowing through the crossbar junction;

V is a voltage across the crossbar junction;

k is the quasi-conductance of the crossbar junction; and

a is a voltage scale factor.

The quasi-conductance, k, and scale factor, a, are parameters determined by the physical properties of crossbar-junction molecules. The scale factor a represents resistive properties of the crossbar junction and can be used to characterize changes in the current flowing through the crossbar junction based on changes in the voltages between the overlapping nanowires. The parameter k is analogous to the conductance, g=1/R, of a linear resistor, where R represents resistance. A nonlinear-tunneling resistor that operates in accordance with the current-voltage equation given above is called a “tunneling resistor.”

FIG. 4 shows a current-versus-voltage curve that represents the operational characteristics of a tunneling resistor located at a crossbar junction. A tunneling resistor located at a nanowire intersection is called a “tunneling-resistor junction.” In FIG. 4, and in subsequent FIG. 5, horizontal line 402 represents a voltage axis, and vertical line 404 represents a current axis. The voltage axis 402 is incremented in volts (V), and the current axis 404 is incremented in microamperes (μA). Curve 406 represents the current versus voltage relationship for a tunneling-resistor junction. The curve 406 shows qualitatively different regions of behavior that are identified as a linear region 408, a first exponential region 410, and a second exponential region 412. In the linear region 408, the tunneling-resistor junction operates as a linear resistor junction with an approximate conductance ka. As the magnitude of the voltage across the tunneling-resistor junction decreases to zero, the resistance of the tunneling-resistor junction is nearly constant, and the magnitude of the current flowing through the tunneling-resistor junction decreases to zero. By contrast, in the exponential regions 410 and 412, the curve 406 shows a nonlinear current-versus-voltage relationship. Applying voltages in the exponential regions 410 and 412 decreases the resistance of a tunneling-resistor junction and exponentially increases the conductance, which allows more current to flow through the tunneling-resistor junction. In FIG. 4, voltages V_D⁻⁻ and V_D⁺ represent the minimum and maximum operating voltages, respectively, that can be applied to the tunneling-resistor junction represented by the curve 406. Applying voltages outside the voltage range [V_D⁻, V_D⁺] destroys the crossbar junction by irreversibly damaging the tunneling-resistor junction molecules, which destroys the usefulness of the electrical connection between overlapping nanowires and renders the tunneling-resistor junction inoperable through being either permanently open or permanently closed.

One particularly important type of tunneling resistor is a reconfigurable nonlinear-tunneling-hysteretic resistor. Using currently available techniques, reconfigurable nonlinear-tunneling-hysteretic resistors can be fabricated at crossbar junctions to produce reconfigurable tunneling-resistor junctions, called “tunneling-hysteretic-resistor junctions.” The resistance of a tunneling-hysteretic-resistor junction can be controlled by applying state-transition voltages that cause the tunneling-hysteretic-resistor junction to alternate between two bistable resistance states. In one resistance state, the tunneling-hysteretic-resistor junction has a relatively low resistance, which corresponds to high-conductance state that is represented by the binary value “1,” and in the other resistance state, the crossbar junction has a relatively high resistance, which corresponds to a low-conductance state that is represented by the binary value “0.”

FIG. 5 shows the operational characteristics of a tunneling-hysteretic-resistor junction and resistance-state transitions under operational control voltages. Curve 506 represents the low-resistance state of the tunneling-hysteretic-resistor junction, and dashed-line curve 508 represents the high-resistance state of the same tunneling-hysteretic-resistor junction. The high-conductance state represented by the curve 506 typically represents a Boolean value or memory state “1,” and the low-conductance state represented by the curve 508 typically represents a Boolean value or memory state “0.” Applying voltages outside the voltage range [V_D⁻, V_D⁺] destroys the tunneling-hysteretic-resistor junction. Voltages V_w1 and V_w0 represent WRITE “1” and WRITE “0” threshold voltages. When the tunneling-hysteretic-resistor junction is in the low-conductance state 508, applying a voltage in the WRITE “1” voltage range [V_w1, V_D⁺] 520 causes the tunneling-hysteretic-resistor junction to transition to the high-conductance state 506, as indicated by directional arrow 512. When the tunneling-hysteretic-resistor junction is in the high-conductance state 506, applying a voltage in the WRITE “0” voltage range [V_D⁻¹,V_w0] 524 causes the tunneling-hysteretic-resistor junction to transition to the low-conductance state 508, as indicated by directional arrow 510.

The tunneling-hysteretic-resistor junction represented in FIG. 5 can be operated as follows. Consider the tunneling-hysteretic-resistor junction initially in a low-conductance state 508. The tunneling-hysteretic-resistor junction can be operated as a low-conductance state resistor by applying voltages in a voltage range [V_D⁻¹,V_w1] 518. However, applying a voltage in the WRITE “1” voltage range 520, causes the tunneling-hysteretic-resistor junction to immediately transition from the low-conductance state 508 to the high-conductance state 506. As a result, the tunneling-hysteretic-resistor junction can now be operated as a high-conductance state resistor by applying voltages in a voltage range [V_w0,V_D⁺] 522. By applying a voltage in the WRITE “0” voltage range 524, the tunneling-hysteretic-resistor junction transitions from the high-conductance state 506 back to the low-conductance state 508. The change in conductance state of a tunneling-hysteretic-resistor junction may be modeled as a change in the junction's quasiconductance k.

Tunneling resistors have a number of properties in common with linear resistors. For example, the total current flowing through a bundle of η parallel linear resistors, each with an identical conductance g, is the sum of the currents flowing through each resistor, and can be represented by a single linear resistor with a conductance ηg. FIG. 6A illustrates a number of parallel tunneling resistors 600, where each tunneling resistor has an identical scale factor a₀ and quasi-conductance k₀. In FIG. 6A, each tunneling resistor 602 provides a path for current to flow from source voltage V_DD 604 to ground 606. The total current, I_total, flowing from the source V_DD 604 to the ground 606 is evenly divided into η paths, each path carrying the same current I. As a result, the total current flowing through the parallel tunneling resistors 600 is given by:
I_Total=ηI=(ηk₀)sin h(a₀V),
which shows that the number of parallel tunneling resistors can be represented by a single equivalent tunneling resistor with the scale factor a₀ and quasi-conductance ηk₀.

Tunneling resistors can also be connected in series and used to fabricate voltage dividers. FIG. 6B illustrates a voltage divider composed of two tunneling resistors. In FIG. 6B, the top tunneling resistor 610 and the bottom tunneling resistor 612 divide the total voltage between the source 604 and the ground 606 as follows:
v_T=v₁+v₂
where v₁ is the voltage across the top resistor 610, and v₂ is the voltage across the bottom resistor 612. The current flowing through the top tunneling resistor 610 equals the current flowing through the bottom tunneling resistor 612 and is represented by:
k₁ sin h(av₁)=k₂ sin h(av₂)
A wire 614 connected to a wire that connects the top tunneling resistor 610 and the bottom tunneling resistor 612 has a voltage equal to the voltage across the tunneling resistor 610 subtracted from the total voltage, v_T−v₁, or, in other words, the voltage across tunneling resistor 612. The voltage carried by the wire 614 is:

v w = 1 a ⁢ tanh - 1 ⁡ ( sinh ⁡ ( av T ) k 2 k 1 + sinh ⁡ ( av T ) )
where the wire 614 is assumed not to be carrying any load.

The nonlinear properties of the tunneling resistors can be used to amplify a current passing through a selected crossbar junction. For example, two identical linear resistors in a series produce twice the resistance. As a result, the current flowing through each of the linear resistors in the series is half of what would flow if the same voltage V was applied across just one of the linear resistors. In other words, substituting a series pair of linear resistors for a single linear resistor reduces the current by one-half.

By contrast, for nonlinear-tunneling resistors operating in the exponential region, substituting a series pair of identical nonlinear-tunneling resistors for a single nonlinear-tunneling resistor has a different result. Each nonlinear-tunneling resistor in the series carries half the voltage, V/2, which results in a drastic reduction in the current by a factor that depends on the voltage V and the parameters of the tunneling resistor. Consider the nonlinear-tunneling resistor represented by the current-versus-voltage curve 406 shown in FIG. 4. Putting a voltage V* 414 across the nonlinear tunneling resistor produces a current I* 416. However, when two of the same nonlinear-tunneling resistors are substituted in a series for the single nonlinear-tunneling resistor, so that each of the nonlinear tunneling resistors receives half the voltage (0.5V*) 418, the current I_SP flows through the series pair, which is due to the nonlinear properties of the nonlinear-tunneling resistor and is considerably smaller than half the current I*, 0.5I* 422. For a numerical example, consider a nonlinear-tunneling resistor with parameters a=3, k=10⁻⁸. Putting a full 3 V drop across the single nonlinear-tunneling resistor produces a current of 40 μA. By contrast, substituting two of the same nonlinear-tunneling resistors in series for the single nonlinear-tunneling resistor results in each of the nonlinear-tunneling resistors carrying 1.5 V and the current flowing through the series pair is 0.45 μA, which is a reduction of the current by about 2 orders of magnitude.

Nanoscale Crossbar-Memory Arrays

In the current subsection, a combined microscale/nanoscale electronic memory device is discussed. FIG. 7 shows a diagram of a combined nanoscale/microscale electronic memory device. The combined microscale/nanoscale electronic memory device 700 interfaces to an external electronic environment through reference voltage signal lines 702 and through two sets of address signal lines 704 and 706. The memory elements within the combined microscale/nanoscale electronic memory device 700 can logically be considered to compose a two-dimensional array, with each memory element specified by a pair of coordinates (x,y), where the x coordinate specifies the column of the two-dimensional array inhabited by the memory element and the y coordinate specifies the row of the two-dimensional array inhabited by the memory element. The set of address signal lines 706 may be used to specify one of 2^p two-dimensional memory-element-array rows, where p is the number of address signal lines in the set of address signal lines 706, and the set of address signal lines 704 specifies one of 2^q columns in the logical, two-dimensional array of memory elements, where q is the number of address signal lines in the set of address signal lines 704. Although the dimensions p and q of the two-dimensional array of memory elements need not be equal, in the following discussion, both dimensions will be assumed to be equal to p, in the interest of notational brevity.

The external sets of address signal lines 704 and 706 are electronically used within the electronic memory device 700 to select a column and row of nanowire-crossbar-memory arrays, and therefore a particular nanowire-crossbar-memory array, and to select a particular row or column within a selected nanowire-crossbar-memory array. For example, in one configuration, the upper three address signal lines 708 of the set of address signal lines 706 may specify one of seven horizontal rows 710-716 of nanowire-crossbar-memory arrays, and the upper three address signal lines 718 of the set of address signal lines 704 may specify one of six vertical columns 720-725 of crossbar-memory systems. The lower three address signal lines 726 in the set of address signal lines. 706 specify a particular row of nanoscale memory elements within a selected crossbar-memory system, and the lower three address signal lines 728 in the set of address signal lines 704 specifies a particular column of nanoscale memory elements within a selected crossbar-memory system. Note that, in general, a larger number of input address signal lines would be employed to address a larger number of columns and rows of crossbar-memory systems than shown in FIG. 7, as well as a larger number of nanoscale-memory-element rows and columns within each crossbar-memory system. The small number of input address lines shown in FIG. 7 is chosen for illustration convenience only.

Each row and column of crossbar-memory systems is accessed through an encoder 730-742. The encoder receives, in FIG. 7, the high-order three input address signal lines and outputs a larger number of microscale signal lines. For example, encoder 737 receives three address signal lines 744 directly interconnected with the high-order input address signal lines 728, and outputs five microscale signal lines 746. The address signal lines output by an encoder pass through all of the crossbar-memory systems within the column or row and are accessed via the encoder. For example, the five microscale signal lines 746 output by the encoder 737 pass through crossbar-memory systems 750-756. Each crossbar-memory system is also connected to two reference voltage signal lines. For example, crossbar-memory system 750 is connected to the reference voltage through reference-voltage signal lines 758 and 760.

The input address signal lines may be microscale address signal lines, or may have even larger dimensions. The microscale signal lines are generally microelectronic or submicroelectronic signal lines and can be produced by currently available photolithographic techniques. The crossbar-memory systems, by contrast, are composed of nanoscale wires, or nanowires. Nanowires have cross-sectional diameters of less than 100 nanometers, while submicroelectronic signal lines have cross-sectional diameters of greater than 100 nanometers. Therefore, there are two nanoscale interconnection interfaces within each crossbar-memory system. In general, the circuitry within the encoders 730-742 is significantly more complex than the circuitry within the crossbar-memory systems. However, each encoder provides access to an entire row or column of crossbar-memory systems, so that only a fraction of the area of an encoder needs to be allocated to any one memory crossbar. As is discussed below, in great detail, defect and fault-tolerant nanoscale interconnection interfaces are facilitated by the supplemental address signal lines output by each encoder.

FIG. 8 shows an abstract representation of a crossbar-memory system within a combined nanoscale/microscale electronic memory device. The crossbar-memory system 800 is composed of a nanowire crossbar 802 with a similarly sized region 804 of horizontally extending nanowires and a similarly sized region 806 of vertically extending nanowires. A vertical column 808 of microscale signal lines passes over the region of horizontally extending nanowires 804, with crossbar junctions interconnecting microscale signal lines with particular horizontal extending nanowires. In alternative embodiments of the present invention, resistive ohmic connections, semi-conductor gate connections, or other types of physical methods at nanowire-crossbar junctions may be employed to determine the signals on the nanowires 804. Similarly, a horizontal set 810 of microscale signal lines passes over the region 806 of vertically extending nanowires, with the horizontal microscale address signal lines selectively interconnected via crossbar junctions, to selected vertically extending nanowires. Each unique pattern of ON and OFF voltages, or, equivalently, HIGH and LOW voltages, on the set of vertical internal microelectronic address signal lines 808 uniquely addresses a particular, horizontally extending nanowire, and places that selected nanowire at a significantly different voltage than the remaining horizontally extending nanowires. Similarly, each different pattern of ON and OFF voltages on the set 810 of horizontal internal microelectronic address signal lines selects a unique vertically extending nanowire, and places that selected vertically extending nanowire at a significantly different voltage than the remaining vertically extending nanowires. The selected horizontally extending nanowire and the selected vertically extending nanowire are interconnected at a single overlap point within the nanowire crossbar 802, and the nanowire-crossbar junction at that overlap point is given a different differential voltage drop than all other nanowire-crossbar junctions within the nanowire crossbar via the pattern of ON and OFF voltages present on the set of vertical and horizontal microscale signal lines 808 and 810.

A variety of different types of nanowire crossbars have been designed and prototyped in laboratories around the world. Different types of nanowire crossbars have different chemical and physical properties at the nanowire-crossbar junctions within the nanowire crossbar 802. Initially, significant efforts were directed to developing diode-like nanowire-crossbar junctions that provide good voltage margins and that prevent many undesirable signal paths within a nanowire crossbar. However, diode-like junctions have proven to be difficult to reliably manufacture. Currently, a large effort is being devoted to designing and fabricating nanowire crossbars with tunneling-hysteretic-resistor junctions.

FIG. 9 illustrates a portion of a grid-like nanowire crossbar 900 featuring tunneling-hysteretic-resistor junctions, as described above with reference to FIG. 5. The nanowire crossbar 900 can be a portion of a crossbar-memory array of a crossbar-memory system. As shown in FIG. 9, the nanowire crossbar comprises a first set of parallel nanowires 902-909 and an overlying, second set of parallel nanowires 910-914 roughly orthogonal to the first set of parallel nanowires 902-909. As shown in FIG. 9, each nanowire of the second set of overlying, parallel nanowires 910-914 is connected to each nanowire of the first set of nanowires 902-909 via a single hysteretic resistor, such as hysteretic resistor 916 interconnecting nanowire 914 with underlying nanowire 904. Each hysteretic resistor has at least two different, stable resistance states. A relatively low-conductance state is arbitrarily assigned the Boolean value or memory state “0,” and a relatively high-conductance state is assigned the Boolean value or memory state “1.” Thus, each hysteretic-resistor nanowire-crossbar junction, or memory element, can store a single bit of information. The resistance state of a tunneling-hysteretic-resistor junction can be reversibly switched from the low-conductance state to the high-conductane state and from the high-conductance state to the low-conductance state by applying a relatively large voltage across the tunneling-hysteretic-resistor junction, as describe above with reference to FIG. 5.

FIG. 10 illustrates the microscale/nanoscale crossbar and encoder of a microscale/nanoscale encoder-demultiplexer that is used, in combination with another microscale/nanoscale encoder-demultiplexer, to address individual nanowire-crossbar junctions of a nanowire crossbar-memory array in nanoscale-memory-array embodiments of the present invention. The encoder 1002 receives an input address a (not shown in FIG. 10) and outputs a nanowire-selection voltage pattern u on a number of microscale signal lines 1004-1010. The microscale signal lines 1004-1010 are selectively interconnected with nanowires, such as nanowire 1014, through nonlinear-tunneling resistors, such as resistive junction 1016, described above with reference to FIG. 4. Unlike in the case of the nanowire crossbar, discussed above with reference to FIG. 9, the resistive microscale/nanoscale junctions of the microscale/nanowire crossbar portion of an encoder-demultiplexer do not need to be reversibly switched between different resistance states. Instead, the pattern of interconnections between microscale signal lines 1004-1010 and nanowires, such as nanowire 1014, result in electronic selection of a single nanowire from among a large number of nanowires that can each be separately addressed by the microscale/nanoscale encoder-demultiplexer. Thus, the nanowire crossbar employed as a nanoscale crossbar-memory array includes nonlinear-tunneling-hysteretic resistors at each junction, the resistance states of which can be reversibly changed in order to store information, while the junctions between microscale output signal lines and nanowires in the microscale/nanowire crossbar of a microscale/nanoscale encoder-demultiplexer are either manufactured to contain nonlinear-tunneling resistors, manufactured to contain no interconnection, or are stably configured at a time after manufacturing.

Mathematical Description of Selected Error-Control Encoding Techniques

Embodiments of the present invention employ concepts derived from well-known techniques in error-control encoding. This subsection provides background information on error-correcting codes, and may be skipped by those familiar with these topics. An excellent reference for this field is the textbook “Error Control Coding: The Fundamentals and Applications,” Lin and Costello, Prentice-Hall, Incorporated, New Jersey, 1983. In this subsection, a brief description of the error-detection and error-correction techniques used in error-control encoding are described. Additional details can be obtained from the above-referenced textbook, or from many other textbooks, papers, and journal articles in this field. The current subsection represents a rather mathematically precise, but concise, description of certain types of error-control encoding techniques. The current invention employs concepts inherent in these error-control encoding techniques for a different purpose.

Error-control encoding techniques systematically introduce supplemental bits or symbols into plain-text messages, or encode plain-text messages using a greater number of bits or symbols than absolutely required, in order to provide information in encoded messages that allows for errors arising in storage or transmission to be detected and, in some cases, corrected. One effect of the supplemental or more-than-absolutely-needed bits or symbols is to increase the distance between valid codewords, when codewords are viewed as vectors in a vector space and the distance between codewords is a metric derived from the vector subtraction of the codewords. The current invention employs concepts used in error-control coding to add supplemental address signal lines to increase the distance between valid addresses in order to correspondingly increase the signal separation, e.g. voltage or current, between ON and OFF states of address signal lines and to provide defective-junction tolerance in interface interconnections. Thus, in the current invention, the plain-text and encoded messages of error-control encoding are analogous to input addresses and coded addresses, and the additional or greater-number-than-needed symbols or bits in error-control encoding are analogous to supplemental or a greater-than-absolutely-needed number of internal address signal lines.

In describing error detection and correction, it is useful to describe the data to be transmitted, stored, and retrieved as one or more messages, where a message μ comprises an ordered sequence of k symbols, μ_i, that are elements of a field F. A message μ can be expressed as:
μ=(μ₀, μ₁, . . . μ_k−1)
The field F is a set that is closed under multiplication and addition, and that includes multiplicative and additive inverses. It is common, in computational error detection and correction, to employ fields comprising a subset of integers with sizes equal to a prime number, with the addition and multiplication operators defined as modulo addition and modulo multiplication. In practice, a binary field, such as {0,1}, is often employed. The original message is encoded into a message c that also comprises an ordered sequence of n elements of the field F, expressed as follows:
c=(c₀,c₁, . . . c_n−1)

Block encoding techniques encode data in blocks. In this discussion, a block can be viewed as a message μ comprising a fixed number of symbols k that is encoded into a message c comprising an ordered sequence of n symbols. The encoded message c generally contains a greater number of symbols than the original message μ, and therefore n is greater than k. The r extra symbols in the encoded message, where r equals n−k, are used to carry redundant check information to allow for errors that arise during transmission, storage, and retrieval to be detected with an extremely high probability of detection and, in many cases, corrected.

In a linear block code, 2^k codewords form a k-dimensional subspace of the vector space of all n-tuples over the field F. The Hamming weight of a codeword is the number of non-zero elements in the codeword, and the Hamming distance between two codewords is the number of elements in which the two codewords differ. For example, consider the following two codewords a and b, assuming elements from the binary field:
a=(10011), and
b=(10001)
The codeword a has a Hamming weight of 3, the codeword b has a Hamming weight of 2, and the Hamming distance between codewords a and b is 1, since codewords a and b differ only in the fourth element. The distance between the two codewords a and b from the binary field can alternatively be defined using the Hamming weight as:
d(a, b)=w(a XOR b)
where w refers to the Hamming weight of the exclusive OR (“XOR”) of codewords a and b, and the Hamming weight can alternatively be can be computed as the Hamming distance between the codeword and an all-0-bit codeword of the same codeword length. Linear block codes are often designated by a three-element tuple [n, k, d_min], where n is the codeword length, k is the message length, or, equivalently, the base-2 logarithm of the number of codewords M, and d_min is the minimum Hamming distance between different codewords, equal to the minimal-Hamming-weight, non-zero codeword in the code.

The encoding of data for transmission, storage, and retrieval, and subsequent decoding of the encoded data, can be notationally described as follows, when no errors arise during the transmission, storage, and retrieval of the data:
μ→c(s)→c(r)→μ
where c(s) is the encoded message prior to transmission, and c(r) is the initially retrieved or received, message. Thus, an initial message μ is encoded to produce encoded message c(s) which is then transmitted, stored, or transmitted and stored, and is then subsequently retrieved or received as initially received message c(r). When not corrupted, the initially received message c(r) is then decoded to produce the original message μ. As indicated above, when no errors arise, the originally encoded message c(s) is equal to the initially received message c(r), and the initially received message c(r) is straightforwardly decoded, without error correction, to the original message μ.

When errors arise during the transmission, storage, or retrieval of an encoded message, message encoding and decoding can be expressed as follows:
μ(s)→c(s)→c(r)→μ(r)
Thus, as stated above, the final message μ(r) may or may not be equal to the initial message μ(s), depending on the fidelity of the error detection and error correction techniques employed to encode the original message μ(s) and decode or reconstruct the initially received message c(r) to produce the final received message μ(r). Error detection is the process of determining that:
c(r)≠c(s)
while error correction is a process that reconstructs the initial, encoded message from a corrupted initially received message:
c(r)→c(s)

The encoding process is a process by which messages, symbolized as μ, are transformed into encoded messages c. Alternatively, a message μ can be considered to be a word comprising an ordered set of symbols from the alphabet consisting of elements of F, and the encoded messages c can be considered to be a codeword also comprising an ordered set of symbols from the alphabet of elements of F. A word μ can be any ordered combination of k symbols selected from the elements of F, while a codeword c is defined as an ordered sequence of n symbols selected from elements of F via the encoding process:
{c:μ→c}

Linear block encoding techniques encode words of length k by considering the word μ to be a vector in a k-dimensional vector space, and multiplying the vector μ by a generator matrix, as follows:
c=μ·G
Notationally expanding the symbols in the above equation produces either of the following alternative expressions:

( c 0 , c 1 , … ⁢ , c n - 1 ) = ( μ 0 , μ 1 , … ⁢ , μ k - 1 ) ⁢ ( g 00 g 01 g 02 ⋯ g 0 , n - 1 ⋮ ⋰ ⋮ g k - 1 , 0 g k - 1 , 1 g k - 1 , 2 ⋯ g k - 1 , n - 1 ) ( c 0 , c 1 , … ⁢ , c n - 1 ) = ( μ 0 , μ 1 , … ⁢ , μ k - 1 ) ⁢ ( g 0 g 1 ⋮ g k - 1 )
where g_i=(g_i,0, g_i,1, g_i,2 . . . g_i,n−1).

The generator matrix G for a linear block code can have the form:

G k , n = ( p 0 , 0 p 0 , 1 ⋯ p 0 , r - 1 1 0 0 … 0 p 1 , 0 p 1 , 1 ⋯ p 1 , r - 1 0 1 0 … 0 ⋮ ⋮ ⋯ 0 0 1 … 0 ⋮ ⋮ ⋯ ⋮ ⋮ ⋮ … ⋮ ⋮ ⋮ ⋯ ⋮ ⋮ ⋮ ⋯ ⋮ p k - 1 , 0 p k - 1 , 1 ⋯ p k - 1 , r - 1 0 0 0 … 1 )
or, alternatively:
G_k,n=[P_k,r|I_k,k].
Thus, the generator matrix G can be placed into a form of a matrix P augmented with a k by k identity matrix I_k,k. A code generated by a generator in this form is referred to as a “systematic code.” When this generator matrix is applied to a word μ, the resulting codeword c has the form:
c=(c₀,c₁, . . . ,c_r−1, μ₀,μ₁, . . . ,μ_k−1)
where c_i=(μ₀p_0,i+μ₁p_1,i, . . . ,μ_k−1p_k−1,i).
Note that, in this discussion, a convention is employed in which the check symbols precede the message symbols. An alternate convention, in which the check symbols follow the message symbols, may also be used, with the parity-check and identity submatrices within the generator matrix interposed to generate codewords conforming to the alternate convention. Thus, in a systematic linear block code, the codewords comprise r parity-check symbols c_i followed by the symbols comprising the original word μ. When no errors arise, the original word, or message μ, occurs in clear-text form within, and is easily extracted from, the corresponding codeword. The parity-check symbols turn out to be linear combinations of the symbols of the original message, or word μ.

One form of a second, useful matrix is the parity-check matrix defined as:
H_r,n=[I_r,r|−P^T]
or, equivalently,

H r , n = ( 1 0 0 … 0 - p 0 , 0 - p 1 , 0 - p 2 , 0 ⋯ - p k - 1 , 0 0 1 0 … 0 - p 0 , 1 - p 1 , 1 - p 2 , 1 ⋯ - p k - 1 , 1 0 0 1 … 0 - p 0 , 2 - p 1 , 2 - p 2 , 2 ⋯ - p k - 1 , 2 ⋮ ⋮ ⋮ ⋯ ⋮ ⋮ ⋮ ⋯ ⋮ 0 0 0 … 1 - p 0 , r - 1 - p 1 , r - 1 - p 0 , r - 1 ⋯ - p k - 1 , r - 1 )
The parity-check matrix can be used for systematic error detection and error correction. Error detection and correction involves computing a syndrome S from an initially received or retrieved message c(r) as follows:
S=(s₀,s₁, . . . ,s_r−1)=c(r)·H^T
where H^T represents the transpose of the parity-check matrix H_r,n expressed as:

H T = ( 1 0 0 ⋯ 0 0 1 0 ⋯ 0 0 0 1 ⋯ 0 ⋮ ⋮ ⋮ ⋯ 1 - p 0 , 0 - p 0 , 1 - p 0 , 2 ⋯ - p 0 , r - 1 - p 1 , 0 - p 0 , 1 - p 0 , 2 ⋯ - p 0 , r - 1 - p 2 , 0 - p 0 , 1 - p 0 , 2 ⋯ - p 0 , r - 1 ⋮ ⋮ ⋮ ⋯ ⋮ - p k - 1 , 0 - p k - 1 , 1 - p k - 1 , 2 ⋯ - p k - 1 , r - 1 )
Note that, when a binary field is employed, x=−x, so the minus signs shown above in H^T are generally not shown.

Hamming codes are linear codes created for error-correction purposes. For any positive integer m greater than or equal to 3, there exists a Hamming code having a codeword length n, a message length k, number of parity-check symbols r, and minimum Hamming distance d_min as follows:
n=2^m−1
k=2^m−m−1
r=n−k=m
d_min=3
The parity-check matrix for a Hamming Code can be expressed as:
H=[I_m|Q]
where I_m is an m×m identity matrix and the submatrix Q comprises all 2^m−m−1 distinct columns which are m-tuples each having 2 or more non-zero elements. For example, for m=3, a parity-check matrix for a [7,4,3] linear block Hamming code is

1. A crossbar-memory system comprising: a first layer of microscale signal lines and a second layer of microscale signal lines; a first layer of one or more nanowires configured so that each first layer nanowire overlaps each first layer microscale signal line; a second layer of one or more nanowires configured so that each second layer nanowire overlaps each second layer microscale signal line and overlaps each first layer nanowire; nonlinear-tunneling resistors configured to selectively connect first layer nanowires to first layer microscale signal lines and to selectively connect second layer nanowires to second layer microscale signal lines; and nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire at each crossbar intersection.

2. The crossbar-memory system of claim 1 further comprising: a first multiplexer configured to multiplex the first layer of one or more nanowires; and a second multiplexer configured to multiplex the second layer of one or more nanowires.

3. The crossbar-memory system of claim 2 wherein the first multiplexer further comprises a first wire that overlaps each first layer nanowire and a nonlinear tunneling-hysteretic resistor connects each first layer nanowire to the first wire, at each overlap point; and the second multiplexer further comprises a second wire that overlaps each second layer nanowire and a nonlinear tunneling-hysteretic resistor connects each first layer nanowire to the second wire, at each overlap point.

4. The crossbar-memory system of claim 1, further comprising: a first encoder connected to the first set of microscale signal lines; and a second encoder connected to the second set of microscale signal lines.

5. The crossbar-memory system of claim 4, wherein the encoders generate an n-bit-code codeword internal address for each different input address received on input signal lines.

6. The crossbar-memory system of claim 1, wherein each microscale signal line carries a voltage corresponding to one bit of an n-bit-code codeword output from a connected encoder.

7. The crossbar-memory system of claim 1, wherein each nanowire in the first layer has an address corresponding to an n-bit-code codeword, and each nanowire in the second layer of one or more nanowires also has an address corresponding to an n-bit-code codeword.

8. The crossbar-memory system of claim 1, wherein each nanowire in the first layer and the second layer has a distinguishable associated n-bit-code codeword internal address.

9. The crossbar-memory system of claim 1, wherein each reconfigurable tunneling-hysteretic resistor has two or more distinguishable conductance states.

10. The crossbar-memory system of claim 9, wherein the multiple conductance states correspond to storing one or more bits of information.