Two-terminal nanotube devices and systems and methods of making same (24-Aug-2010)

RELATED APPLICATIONS

This application is related to the following references, which are assigned to the assignee of this application and are hereby incorporated by reference herein in their entireties:

Electromechanical Memory Array Using Nanotube Ribbons and Method for Making Same (U.S. patent application Ser. No. 09/915,093, now U.S. Pat. No. 6,919,592), filed on Jul. 25, 2001;

Electromechanical Memory Having Cell Selection Circuitry Constructed With NT Technology (U.S. patent application Ser. No. 09/915,173, now U.S. Pat. No. 6,643,165), filed on Jul. 25, 2001;

Hybrid Circuit Having NT Electromechanical Memory (U.S. patent application Ser. No. 09/915,095, now U.S. Pat. No. 6,574,130), filed on Jul. 25, 2001;

Electromechanical Three-Trace Junction Devices (U.S. patent application Ser. No. 10/033,323, now U.S. Pat. No. 6,911,682), filed on Dec. 28, 2001;

Methods of Making Electromechanical Three-Trace Junction Devices (U.S. patent application Ser. No. 10/033,032, now U.S. Pat. No. 6,784,028), filed on Dec. 28, 2001;

Nanotube Films and Articles (U.S. patent application Ser. No. 10/128,118, now U.S. Pat. No. 6,706,402), filed on Apr. 23, 2002;

Methods of Nanotube Films and Articles (U.S. patent application Ser. No. 10/128,117, now U.S. Pat. No. 6,835,591), filed Apr. 23, 2002;

Methods of Making Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (U.S. patent application Ser. No. 10/341,005), filed on Jan. 13, 2003;

Methods of Using Thin Metal Layers to Make Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (U.S. patent application Ser. No. 10/341,055), filed Jan. 13, 2003;

Methods of Using Pre-formed Nanotubes to Make Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (U.S. patent application Ser. No. 10/341,054), filed Jan. 13, 2003;

Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (U.S. patent application Ser. No. 10/341,130), filed Jan. 13, 2003;

Non-volatile Electromechanical Field Effect Devices and Circuits using Same and Methods of Forming Same (U.S. patent application Ser. No. 10/864,186), filed Jun. 9, 2004;

Devices Having Horizontally-Disposed Nanofabric Articles and Methods of Making the Same, (U.S. patent application Ser. No. 10/776,059, U.S. Patent Publication No. 2004/0181630), filed Feb. 11, 2004;

Devices Having Vertically-Disposed Nanofabric Articles and Methods of Making the Same (U.S. patent application Ser. No. 10/776,572, U.S. Patent Publication No. 2004/0175856), filed Feb. 11, 2004; and

Patterned Nanoscopic Articles and Methods of Making the Same (U.S. patent application Ser. No. 10/936,119, U.S. Patent Publication No. 2005/0128788).

BACKGROUND

1. Technical Field

The present application is generally related to the field of switching devices and, more specifically, to two terminal nanotube devices that may be used to make nonvolatile and other memory circuits.

2. Discussion of Related Art

Digital logic circuits are used in personal computers, portable electronic devices such as personal organizers and calculators, electronic entertainment devices, and in control circuits for appliances, telephone switching systems, automobiles, aircraft and other items of manufacture. Early digital logic was constructed out of discrete switching elements composed of individual bipolar transistors. With the invention of the bipolar integrated circuit, large numbers of individual switching elements could be combined on a single silicon substrate to create complete digital logic circuits such as inverters, NAND gates, NOR gates, flip-flops, adders, etc. However, the density of bipolar digital integrated circuits is limited by their high power consumption and the ability of packaging technology to dissipate the heat produced while the circuits are operating. The availability of metal oxide semiconductor (“MOS”) integrated circuits using field effect transistor (“FET”) switching elements significantly reduces the power consumption of digital logic and enables the construction of the high density, complex digital circuits used in current technology. The density and operating speed of MOS digital circuits are still limited by the need to dissipate the heat produced when the device is operating.

Digital logic integrated circuits constructed from bipolar or MOS devices do not function correctly under conditions of high heat or extreme environment. Current digital integrated circuits are normally designed to operate at temperatures less than 100 degrees centigrade and few operate at temperatures over 200 degrees centigrade. In conventional integrated circuits, the leakage current of the individual switching elements in the “off” state increases rapidly with temperature. As leakage current increases, the operating temperature of the device rises, the power consumed by the circuit increases, and the difficulty of discriminating the off state from the on state reduces circuit reliability. Conventional digital logic circuits also short internally when subjected to extreme environment because they may generate electrical currents inside the semiconductor material. It is possible to manufacture integrated circuits with special devices and isolation techniques so that they remain operational when exposed to extreme environment, but the high cost of these devices limits their availability and practicality. In addition, such digital circuits exhibit timing differences from their normal counterparts, requiring additional design verification to add protection to an existing design.

Integrated circuits constructed from either bipolar or FET switching elements are volatile. They only maintain their internal logical state while power is applied to the device. When power is removed, the internal state is lost unless some type of non-volatile memory circuit, such as EEPROM (electrically erasable programmable read-only memory), is added internal or external to the device to maintain the logical state. Even if non-volatile memory is utilized to maintain the logical state, additional circuitry is necessary to transfer the digital logic state to the memory before power is lost, and to restore the state of the individual logic circuits when power is restored to the device. Alternative solutions to avoid losing information in volatile digital circuits, such as battery backup, also add cost and complexity to digital designs.

Important characteristics for logic circuits in an electronic device are low cost, high density, low power, and high speed. Conventional logic solutions are limited to silicon substrates, but logic circuits built on other substrates would allow logic devices to be integrated directly into many manufactured products in a single step, further reducing cost.

Devices have been proposed which use nanoscopic wires, such as single-walled carbon nanotubes, to form crossbar junctions to serve as memory cells. (See WO 01/03208, Nanoscopic Wire-Based Devices, Arrays, and Methods of Their Manufacture; and Thomas Rueckes et al., “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing,” Science, vol. 289, pp. 94-97, 7 Jul. 2000.) Hereinafter these devices are called nanotube wire crossbar memories (NTWCMs). Under these proposals, individual single-walled nanotube wires suspended over other wires define memory cells. Electrical signals are written to one or both wires to cause them to physically attract or repel relative to one another. Each physical state (i.e., attracted or repelled wires) corresponds to an electrical state. Repelled wires are an open circuit junction. Attracted wires are a closed state forming a rectified junction. When electrical power is removed from the junction, the wires retain their physical (and thus electrical) state thereby forming a non-volatile memory cell.

U.S. Pat. No. 6,919,592, entitled “Electromechanical Memory Array Using Nanotube Ribbons and Method for Making Same” discloses, among other things, electromechanical circuits, such as memory cells, in which circuits include a structure having electrically conductive traces and supports extending from a surface of a substrate. Nanotube ribbons that can electromechanically deform, or switch are suspended by the supports that cross the electrically conductive traces. Each ribbon comprises one or more nanotubes. The ribbons are typically formed from selectively removing material from a layer or matted fabric of nanotubes.

For example, as disclosed in U.S. Pat. No. 6,919,592, a nanofabric may be patterned into ribbons, and the ribbons can be used as a component to create non-volatile electromechanical memory cells. The ribbon is electromechanically-deflectable in response to electrical stimulus of control traces and/or the ribbon. The deflected, physical state of the ribbon may be made to represent a corresponding information state. The deflected, physical state has non-volatile properties, meaning the ribbon retains its physical (and therefore informational) state even if power to the memory cell is removed. As disclosed in U.S. Pat. No. 6,911,682, entitled “Electromechanical Three-Trace Junction Devices,” three-trace architectures may be used for electromechanical memory cells, in which the two of the traces are electrodes to control the deflection of the ribbon.

The use of an electromechanical bi-stable device for digital information storage has also been suggested (See U.S. Pat. No. 4,979,149, entitled “Non-volatile Memory Device Including a Micro-Mechanical Storage Element”).

The creation and operation of bi-stable, nano-electro-mechanical switches based on carbon nanotubes (including mono-layers constructed thereof) and metal electrodes has been detailed in earlier patent applications having a common assignee as the present application, U.S. Pat. Nos. 6,784,028, 6,835,591, 6,574,130, 6,643,165, 6,706,402, 6,919,592, 6,911,682, and 6,924,538; U.S. Patent Publication Nos. 2005-0062035, 2005-0035367, 2005-0036365, 2004-0181630; and U.S. patent application Ser. Nos. 10/341,005, 10/341,055, 10/341,054, 10/341,130, the contents of which are hereby incorporated by reference in their entireties (hereinafter and hereinbefore the “incorporated patent references”).

SUMMARY

The present invention provides structures and methods of making two-terminal nanotube switches, arrays of memory cells based on these switches, fuse/antifuse devices based on these switches, and reprogrammable wiring based on these switches.

Under one aspect, a two terminal switching device includes a first conductive terminal and a second conductive terminal in spaced relation to the first terminal. The device also includes a nanotube article having at least one nanotube. The article is arranged to overlap at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals. The stimulus circuit is capable of applying a first electrical stimulus to at least one of the first and second terminals to change the resistance of the device between the first and second terminals from a relatively low resistance to a relatively high resistance, and is capable of applying a second electrical stimulus to at least one of the first and second terminals to change the resistance of the device between the first and second terminals from a relatively high resistance to a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device. The first and second states of the device may be nonvolatile. The resistance of the first state may be at least about ten times larger than the resistance of the second state.

Under another aspect, the nanotube article overlaps at least a portion of the first terminal with a controlled geometrical relationship. The controlled geometrical relationship may allow electrical current to flow relatively well between the first terminal to the nanotube article, and allow heat to flow relatively poorly between the first terminal and the nanotube article. The controlled geometrical relationship may be a predetermined extent of overlap. Under another aspect, at least one of the first and second terminals has a vertically oriented feature, and the nanotube article substantially conforms to at least a portion of the vertically oriented feature. Under another aspect, the nanotube article includes a region of nanotube fabric of defined orientation.

Under another aspect, the first electrical stimulus is an erase operation. Under another aspect, the second electrical stimulus is a program operation. Under another aspect, the stimulus circuit is capable of applying a third electrical stimulus to at least one of the first and second terminals to determine the state of the device. The third electrical stimulus may be a non-destructive read-out operation.

Under another aspect, a two-terminal memory device includes a first conductive terminal and a second conductive terminal in spaced relation to the first conductive terminal. The device also includes a nanotube article having at least one nanotube. The article is arranged to overlap at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals. The stimulus circuit is capable of applying a first electrical stimulus to at least one of the first and second terminals to open one or more gaps between one or more nanotubes and one or more conductors in the device. The opening of one or more gaps changes the resistance of the device between the first and second terminals from a relatively low resistance to a relatively high resistance. The stimulus circuit is also capable of applying a second electrical stimulus to at least one of the first and second terminals to close one or more gaps between one or more nanotubes and one or more conductors in the device. The closing of one or more gaps changes the resistance of the device between the first and second terminals from a relatively high resistance to a relatively low resistance. A conductor in the device comprises one or more of the first terminal, the second terminal, a nanotube, and a nanotube segment. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device. The first and second states of the device may be nonvolatile.

Under another aspect, the first electrical stimulus overheats at least a portion of the nanotube article to open one or more gaps. Under another aspect, one or more thermal characteristics of the device are selected to minimize a flow of heat out of the nanotube element. The flow of heat out of the nanotube element may be minimized by arranging the nanotube article and the first terminal with a controlled geometrical relationship that limits heat flow out of the nanotube article and into the first terminals. The controlled geometrical relationship may be a predetermined extent of overlap. The flow of heat out of the nanotube element may be minimized by selecting a material for the first terminal that conducts electricity relatively well and conducts heat relatively poorly. The material may have a relatively high electrical conductivity and a relatively low thermal conductivity.

Under another aspect, the first electrical stimulus opens one or more gaps by forming a gap between one or more nanotubes and one or more of the first and second terminals. Under another aspect, the first electrical stimulus opens one or more gaps by separating one or more nanotubes from one or more other nanotubes in an electrical network of nanotubes. Under another aspect, the first electrical stimulus opens one or more gaps by breaking one or more nanotubes into two or more nanotube segments. Under another aspect, the first electrical stimulus opens one or more gaps by exciting one or more phonon modes of one or more nanotubes in the nanotube article. The one or more phonon modes may behave as a thermal bottleneck. The one or more phonon modes may be optical phonon modes. One or more nanotubes in the nanotube article may selected to have a particularly strong radial breathing mode, or a defect mode. Under another aspect, the second electrical stimulus closes one or more gaps by attracting one or more nanotubes to one or more conductors. The second electrical stimulus may attract one or more nanotubes to one or more conductors by generating an electrostatic attraction.

Under another aspect, a selectable memory cell includes a cell selection transistor including a gate, a source, and a drain, with the gate in electrical contact with one of a word line and a bit line, and a drain in electrical contact with the other of the word line and the bit line. The cell also includes a two-terminal switching device, which includes a first conductive terminal, a second conductive terminal, and a nanotube article having at least one nanotube and overlapping at least a portion of each of the first and second terminals. The first terminal is in electrical contact with the source of the cell selection transistor and the second terminal is in electrical contact with a program/erase/read line. The cell also includes a memory operation circuit in electrical communication with the word line, bit line, and program/erase/read line. The memory operation circuit is capable of applying a select signal on the word line to select the cell and an erase signal on the program/erase/read line to change the resistance of the device between the first and second terminals from a relatively low resistance to a relatively high resistance. The memory operation circuit is also capable of applying a select signal on the word line to select the cell and a program signal on the program/erase/read line to change the resistance of the device between the first and second terminals from a relatively high resistance to a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first informational state of the memory cell, and the relatively high resistance between the first and second conductive elements corresponds to a second informational state of the memory cell. The first and second informational states may be nonvolatile.

Under another aspect, the memory operation circuit applies a select signal on the word line to select the cell and a read signal on the program/erase/read line to determine the informational state of the memory cell. Determining the informational state of the memory cell may not change the state of the memory cell. Under another aspect, a plurality of selectable memory cells are connected to the program/erase/read line.

Under another aspect, a reprogrammable two-terminal fuse-antifuse device includes a first conductor, a second conductor in spaced relation to the first conductor, and a nanotube element having at least one nanotube and overlapping at least a portion of each of the first and second conductors. The nanotube element is capable of opening an electrical connection between the first and second conductors in response to a first threshold voltage across the first and second conductors to form a first device state. The nanotube element is also capable of closing an electrical connection between the first and second conductors in response to a second threshold voltage across the first and second conductors to form a second device state. The device may be a cross-point switch. The first and second device states may be nonvolatile.

Under another aspect, a reprogrammable interconnection between a plurality of wiring layers includes a first conductive terminal and a plurality of wiring layers, each of which includes a wiring layer conductive terminal. The interconnection also includes a stimulus circuit in electrical communication with the first conductive terminal and with each wiring layer conductive terminal. The interconnection also includes a nanotube article having at least one nanotube. The nanotube article is arranged to overlap at least a portion of the first conductive terminal and at least a portion of each wiring layer conductive terminal. The stimulus circuit is capable of applying a first electrical stimulus to cause the nanotube article to form an interconnection between two wiring layers of the plurality of wiring layers. The stimulus circuit is also capable of applying a second electrical stimulus to cause the nanotube article to break an interconnection between two wiring layers of the plurality of wiring layers. Under another aspect, the stimulus circuit breaks all interconnections in response to a security concern.

Under another aspect, a method of making a two terminal memory device includes providing a first conductive terminal, and providing a second conductive terminal in spaced relation to the first terminal. The method also includes providing a stimulus circuit in electrical communication with at least one of the first and second terminals. The method also includes providing a nanotube article comprising at least one nanotube. The nanotube article overlaps by a predetermined extent at least a portion of at least one of the first and second terminals. The device response is a function of the predetermined extent of overlap between the nanotube article and the at least one of the first and second terminals.

The predetermined extent of overlap may be determined by a timed isotropic etch procedure. The predetermined extent of overlap may be determined by a directional etch procedure. The predetermined extent of overlap may be determined by a thickness of a sacrificial film. The predetermined extent of overlap may be determined by a thickness of the at least one of the first and second terminals.

Under another aspect, the method includes fabricating a second memory device, which has a structure that is a mirror image of a structure of the two terminal memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

In the Drawing,

FIG. 1A illustrates a cross sectional view of an exemplary embodiment of the present invention;

FIG. 1B illustrates a cross sectional view of an exemplary embodiment of the present invention;

FIGS. 2A-I are SEM micrographs of structures according to certain embodiments of the invention;

FIGS. 3A-E illustrate cross sectional views of structures according to certain embodiments of the invention;

FIG. 4 is a cross sectional view of a structure according to certain embodiments of the invention;

FIG. 5 is a cross sectional view of a structure according to certain embodiments of the invention;

FIG. 6 is a cross sectional view of a structure according to certain embodiments of the invention;

FIG. 7 is a flow chart illustrating general fabrication processes according to certain embodiments of the invention;

FIGS. 8A-F illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIGS. 9A-C illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIGS. 10A-I illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIGS. 11A-C illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIGS. 12A, B and 13 illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIGS. 14A-J illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIGS. 15A-N illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIGS. 16A-L illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIGS. 17A-M illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIG. 18 is a flow chart illustrating switch operability verification using read, erase, and programming cycles according to certain embodiments of the invention;

FIG. 19 is a flow chart illustrating erase cycles according to certain embodiments of the invention;

FIG. 20 is a graph illustrating current and voltage erase characteristics of devices according to certain embodiments of the invention;

FIG. 21 is a flow chart illustrating programming cycles according to certain embodiments of the invention;

FIGS. 22A and 22B are graphs illustrating read, erase, and program current and voltage characteristics and resistance characteristics, respectively, of devices according to certain embodiments of the invention;

FIGS. 23A-E, 24A-E and 25A-E illustrate cross-sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIG. 26 is a cross sectional view of a structure according to certain embodiments of the invention;

FIG. 27 is a cross sectional view of a structure according to certain embodiments of the invention;

FIG. 28 is a cross sectional view of a structure according to certain embodiments of the invention;

FIG. 29 is a cross sectional view of a structure according to one aspect of the present invention;

FIGS. 30A and 30B illustrate schematics of prior art structures;

FIG. 31 illustrates a cross section of a device according to certain embodiments of the invention;

FIGS. 32A and 32B illustrate schematic diagrams according to certain embodiments of the invention;

FIGS. 33A-G illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention;

FIGS. 34A-E illustrate cross sectional views of structures created during fabrication steps according to certain embodiments of the invention; and

FIGS. 35 and 36 are plan views of structures according to certain embodiments of the invention.

DETAILED DESCRIPTION

Preferred embodiments of the present invention provide two-terminal nanotube switches, and a number of devices using those switches. In general, a nanotube element or article overlaps at least a portion of each of two terminals, e.g., conductive elements. A stimulus circuit, connected to one or both of the terminals, applies appropriate electrical stimulus to which the nanotube element responds by changing the state of the switch. For example, the resistance of an electrical pathway between the two terminals characterizes the state of the switch. A relatively high resistance pathway corresponds to an “open” or OFF state of the switch, and a relatively low resistance pathway corresponds to a “closed” or ON state of the switch. The two states are non-volatile. The stimulus circuit can non-destructively read-out (NDRO) the state of the switch, and can change the state (e.g., resistance) of the switch repeatedly.

The inventors believe that the ability to change the switch between the two states is related to a relationship between the thermal and electrical characteristics of the switch. More specifically, the inventors believe that the performance of the switch is related to a relationship between the electrical current that passes through the nanotube element and the dissipation of heat out of the nanotube element. Desirably, in order to change the switch to the “open” state, the stimulus circuit applies a stimulation that is, the inventors believe, large enough to cause overheating in the nanotube element, and at the same time the switch has design characteristics that limit the amount of current-induced heat that can flow out of the nanotube element. The inventors believe that this allows the overheating of the nanotube element, which breaks conductive paths in the switch and creates the “open” state. In other words, the inventors believe that thermal and electrical management of the switch enhance the buildup of heat in the nanotube element, so that an “open” state can be formed. In some embodiments, thermal and electrical management is accomplished by overlapping the nanotube article with at least one of two terminals, e.g., conductive elements, in a predetermined, controlled way. For example, in some embodiments, the nanotube element overlaps at least one of the two terminals with a specified geometry, e.g., a controlled overlap length of a preferred length. Then heat flows poorly from the nanotube element into the terminal, but the length of contact is long enough that current flows well from the terminal into the nanotube element. In some embodiments, thermal and electrical management is accomplished by fabricating the switch from selected materials that dissipate heat particularly poorly. For example, the switch can be passivated with a layer that has a low thermal conductivity, which helps to trap heat in the nanotube element. Or, the terminals can be fabricated from a material that has a relatively good electrical conductivity and a relatively poor thermal conductivity. Other designs and materials for thermal and electrical management of the switch are contemplated. It should be noted that while changes in the resistance of the switch due to electrical stimulation have been repeatedly observed, that the causes of these resistance changes are still being considered from both a theoretical and experimental standpoint. At the time of filing, it is the inventors' belief that thermal effects as described herein may cause or contribute to the observed behavior. Other effects may also cause or contribute the observed behavior.

The switch can be fabricated using methods that are easily integrated into existing semiconductor fabrication methods, as described in greater detail below. Several methods that allow the fabrication of an overlap of specified geometry between the nanotube article or element and a terminal are described in detail.

Because the switch can be controllably switched between two non-volatile states, and because the fabrication of the switch can be integrated into existing semiconductor fabrication methods, the switch is useful in a number of applications. For example, the switch can be implemented in non-volatile random access memory (NRAM) arrays, reprogrammable fuse/antifuse devices, and in reprogrammable wiring applications.

First, embodiments of nanotube-based nonvolatile memory devices/switches will be shown, and their various components will be described. Next, methods of fabricating switching elements will be illustrated. Methods of testing as-fabricated switching elements will be described. Last, embodiments of devices that utilize nanofabric-based nonvolatile elements, such as memory arrays, fuse/antifuse devices, and reprogrammable wiring, and methods of making same, will be illustrated.

2-Terminal Nanotube Switches

FIG. 1A illustrates a cross sectional representation of nonvolatile 2-terminal nanotube switch (2-TNS) 10. Nanotube element 25 is disposed on substrate 35, which includes a layer of insulator 30. Nanotube element 25 at least partially overlaps two terminals, e.g., conductive elements 15 and 20, which are both deposited directly onto nanotube element 25.

In this embodiment, nanotube element 25 is patterned within a region that can be defined before or after deposition of conductive elements 15 and/or 20.

Conductive elements 15 and 20 are in contact with a stimulus circuit 100. Stimulus circuit 100 electrically stimulates at least one of conductive elements 15 and 20, which changes the state of switch 10. More specifically, nanotube element 25 responds to the stimulation by changing the resistance of switch 10 between the conductive elements 15 and 20; the relative value of the resistance corresponds to the state of the switch. For example, if stimulus circuit 100 applies a relatively high voltage and relatively high current across conductive elements 15 and 20, then nanotube element 25 responds by changing the resistance of the switch between conductive elements 15 and 20 to a relatively high resistance. This corresponds to an “erased” state of the device, where electrical conduction is relatively poor between conductive elements 15 and 20. For example, if stimulus circuit 100 applies a relatively low voltage and relatively low current across conductive elements 15 and 20, then nanotube element 25 responds by changing the resistance of the switch between conductive elements 15 and 20 to a relatively low resistance. This corresponds to a “programmed” state of the device, where electrical conduction is relatively good, or even near-ohmic, between conductive elements 15 and 20. Generally it is preferable that the values of the high and low resistances are separated by at least an order of magnitude. Example voltages, currents, and resistances for “programmed” and “erased” switch states for some embodiments of two-terminal nanotube switches are described in greater detail below.

Conductive elements 15 and 20 are preferably made of a conductive material, and can be made of the same or different materials depending on the desired performance characteristics of switch 10. Conductive elements 15 and 20 can, for example, be composed of metals such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, as well as other suitable metals, and combinations of these. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, including CNTs themselves (single walled, multiwalled, and/or double walled, for example), or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_x and TiSi_x may be used. Other kinds of conductor, or semiconductor, materials can also be used. Conductive elements 15 and 20 generally have a thickness in the range of 5 to 500 nm, for example. In this embodiment, conductive elements 15 and 20 are preferably separated by about 160 nm. The separation can be as small or as large as allowed by process design, for example from 5 nm up to 1 micron, depending on the desired characteristics of switch 10. Preferably the separation is less than about 250 nm.

Preferred methods of fabricating a full overlap between a nanotube element and a terminal, or conductive element, follow well known techniques described in patent publications and issued patents listed above and commonly assigned to the assignee of the present application, or are currently used in present-day electronic industry practices. Preferred methods of fabricating a partial overlap between a nanotube element and a terminal, or conductive element, of a controlled overlap length are described in greater detail below.

Insulator 30 may be composed of SiO₂, SiN, Al₂O₃, BeO, polyimide, or other suitable insulating material, and have a thickness in the range of 2 to 500 nm, for example. Insulator 30 is supported by substrate 35, made from silicon for example. Substrate 35 may also be a composite of semiconductors, insulators, and/or metals that connect to conductive elements 15 and 20 to supply electrical signals to nonvolatile 2-terminal nanotube switch (2-TNS) 10 as illustrated further below. In some embodiments, substrate 35 may be of the same material as insulator 30, e.g. quartz. In general, the substrate 35 may be any material that will accept the deposition of nanotubes by spin coating, but preferably a material chosen from the group consisting of a thermal oxide or nitride, including but not limited to silicon dioxide, silicon nitride, alumina on silicon, or any combination of the following on silicon or silicon dioxide: aluminum, molybdenum, iron, titanium, platinum, and aluminum oxide, or any other substrate useful in the semiconductor industry.

In some embodiments, nanotube element 25 is a fabric of matted carbon nanotubes (also referred to as a nanofabric). Methods of making nanotube elements and nanofabrics are known and are described in the incorporated patent references. In some embodiments, the nanotube element or fabric is porous, and material from conductive elements 15 and/or 20 fills at least some of the pores in the nanotube element. In some embodiments, nanotube element 25 includes single-walled nanotubes (SWNTs) and/or multi-walled nanotubes (MWNTs). In some preferred embodiments, the nanotube element 25 includes double walled nanotubes (DWNT). In some preferred embodiments, nanotube element 25 includes one or more bundles of nanotubes. In some preferred embodiments, nanotube element 25 includes one or more bundles of DWNTs. In some embodiments, nanotube element 25 includes SWNTs, MWNTs, nanotube bundles, and a large proportion of DWNTs. In some embodiments, nanotube element 25 includes a single nanotube.

Some nanotubes fabricated by some methods are preferred for use in 2-TNS 10. For example, nanotubes produced by CVD processes are preferred, e.g., they tend to consistently exhibit the switching behavior described herein.

FIG. 2A shows an SEM image of an example SWNT nanofabric 50 that is fabricated with a spin-on method as a substantially single layer of matted nanotubes. While FIG. 2A illustrates a nanofabric that is a monolayer, multiple layers of nanofabric may be fabricated with other appropriate techniques. That is, preferred embodiments do not require a nanofabric that is necessarily a monolayer of nanotubes. For example, the nanofabric can include bundles of nanotubes and/or single nanotubes. While FIG. 2A shows a nanofabric having randomly oriented nanotubes, aligned or nearly aligned nanotubes may be used as well. Also, the nanotubes can be metallic and/or semiconducting, as described in the incorporated patent references. In general, the nanofabric need not include carbon nanotubes at all, but simply needs to be made of a material and have a form that exhibits nonvolatile switching behavior as described herein, e.g. silicon nanowire based fabrics, other nanowires or quantum dots.

The nanofabric shown in FIG. 2A is preferably fabricated on a horizontal surface. In general, fabrics are conformal and may be oriented at various angles, without limitations. FIG. 2C is an SEM image of structure 90 with nanofabric 95 conforming to an underlying step after deposition. These conformal properties of nanofabrics may be used to fabricate vertically oriented 2-TNS with enhanced dimensional control and requiring less area (e.g. can be fabricated at greater density) as illustrated further below.

In some embodiments, nanotube element 25 in FIG. 1A is a SWNT nanofabric with a thickness between 0.5 to 5 nm. In other embodiments nanotube element 25 in FIG. 1A is a MWNT nanofabric with a thickness between 5 to 20 nm. SWNT diameters may be in the range of 0.5 to 1.5 nm, for example. Individual nanotubes may have a length in the 0.3 to 4 um range, and thus can be long enough to span the separation between conductive elements 15 and 20. Nanotubes may also be shorter than the distance between conductive elements 15 and 20 but contact (or “network with”) other nanotubes to span the separation between the elements. See U.S. Pat. No. 6,706,402, entitled “Nanotube Films and Articles” for details of conductive articles and networks formed from nanotubes. In general, the nanotube density should be high enough to ensure that at least one nanotube or network of nanotubes spans the entire distance between conductive elements 15 and 20. Other preferred characteristics for nanotubes are described herein.

The two-terminal nanotube switch 10 illustrated in FIG. 1A has a pathway between conductive elements 15 and 20 that can be in one of two states. One state is characterized by a pathway that has a relatively high resistance, R_HIGH between conductive elements 15 and 20. Current generally flows poorly between conductive elements 15 and 20 in this “open,” “erased”, or OFF state. The other state is characterized by a pathway that has a relatively low resistance, R_LOW between conductive elements 15 and 20. Current generally flows easily between conductive elements 15 and 20 in this “closed,” “programmed,” or ON state.

Switch 10 is typically fabricated in the low-resistance state. The resistance of this state depends on the characteristics of nanotube element 25 and of conductive elements 15 and 20. The inherent resistance of nanotube element 25, and nanofabrics in general, can be controlled to be in the range of 100 to 100,000 ohms per square, for example, as measured by four-point probe measurements. Films with resistances between 1,000 to 10,000 ohms per square typically have a density of 250 to 500 nanotubes per square micron. In some embodiments nanotube element 25 preferably has, for example, between 1 and 30 nanotubes. In some embodiments nanotube element preferably has 5 to 20 nanotubes.

The total resistance of switch 10 between conductive elements 15 and 20 in the “closed” state includes the contact resistance of each overlap region in series, plus the inherent series resistance of the nanotube, divided by the number of nanotube pathways (which may be single nanotubes and/or networks of nanotubes) between elements 15 and 20. In some preferred embodiments, the total as-fabricated resistance of 2-TNS 10 is typically in the range of 10 kΩ to 40 kΩ. In other preferred embodiments, the switch can be designed such that the resistance is less than 100Ω or greater than 100 kΩ. An explanation of nanotube resistance may be found in the reference N. Srivastava and K. Banerjee, “A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies”, Proceedings of the 21^st International VLSI Multilevel Interconnect Conference (VMIC), Sep. 29-Oct. 2, 1004, Wikoloa, Hi., pp. 393-398.

In general, the device performance does not vary strongly with the density of nanotubes in the nanotube element. For example, the sheet resistance of the nanofabric can vary by a factor of at least 10, and the device performs equally well. In a preferred embodiment, the sheet resistance of the nanofabric is below approximately 1 kΩ. In some embodiments, the resistance of the nanofabric is assessed after fabrication, and if the resistance is found to be greater than approximately 1 kΩ, then additional nanofabric is deposited with a density sufficient to lower the resistance below about 1 kΩ.

Stimulus circuit 100 applies appropriate electrical stimulation to at least one of conductive elements 15 and 20 to switch 2-TNS 10 between the low resistance and high resistance states. In general, the appropriate electrical stimulation to 2-TNS 10 depends on the particular embodiment of the switch. For example, in some embodiments, stimulus circuit 100 can change switch 10 to the high resistance “open” state by applying a relatively high voltage bias across conductive elements 15 and 20 with unrestricted current. In some embodiments, this voltage is about 8-10 V, or about 5-8 V, or 3-5 V, or less. Sometimes, the electrical stimulation is a voltage pulse, and sometimes a series of pulses is used to switch 2-TNS 10 to the “open” state, for example a series of one or more pulses between 1-5 V. The duration of one or more pulses may also be varied to switch 2-TNS 10 to the “open” state. It has been found in some embodiments that allowing a relatively high current e.g. greater than 50 uA to flow through the switch can enhance its ability to switch to the “open” state. In some embodiments, stimulus circuit 100 must apply a stimulation that exceeds a critical voltage and/or current in order to switch 2-TNS 10 to an “open” state. In general, any electrical stimulation that is sufficient to cause 2-TNS 10 to switch to a relatively high resistance state can be used. In some embodiments, the state is characterized by a resistance R_HIGH on the order of 1 GΩ or more. In general, the state can also be considered to be characterized by a relatively high impedance.

In some embodiments, stimulus circuit 100 can change switch 10 to the low resistance “closed” state by applying a relatively voltage bias across conductive elements 15 and 20. In some embodiments, a voltage of about 3-5 V, or about 1-3 V, or less, switches 2-TNS to the low-resistance state. In some cases, the electrical stimulation required to switch 2-TNS 10 to a “closed” state depends in part on the electrical stimulation that was used to switch 2-TNS 10 to an “open” state. For example, if a relatively high voltage bias was used to “open” the switch, then a relatively high voltage bias may be needed to “close” the switch. For example, if an 8-10 V pulse is used to “open” the switch, then a 3-5 V pulse may be needed to “close” the switch. If 3-5 V pulse is used to “open” the switch, then a 1-2 V pulse may be needed to “close” the switch. In general, the stimulation used to “open” and “close” the switch can vary each time, although the “close” stimulation depends in part on the “open” stimulation. In other words, even though the switch is “opened” for example with an 8-10 V pulse, and then “closed” with a 3-5 V pulse, the switch can subsequently be “opened” again with a 3-5 V pulse and “closed” with a 1-2 V pulse. Greater voltages used to open the switch lead to greater voltages to close the switch. Although the examples listed here use “open” voltages that are higher than the “close” voltages, in some embodiments the “close” voltages may be higher than the “open” voltages. A distinction between close and open operations relies more on current control than on voltage amplitude. As an example: a 6V erase pulse without current restriction can be used to open the switch and subsequently, an 8V program pulse with a current cap of 1 uA can be used to close the switch.

Sometimes, the electrical stimulation is a voltage pulse, and sometimes a series of pulses is used to switch 2-TNS 10 to the “closed” state, for example a series of one or more pulses between 1-5 V. The duration of one or more pulses may also be varied to cause 2-TNS 10 to switch to the “closed” state. In some embodiments, the same voltage level can be used to “close” and “open” the switch, but the waveforms of the two stimuli are different. For example, a series of pulses at a given voltage could be used to “open” the switch, and a single pulse at the same or a similar voltage could be used to “close” the switch. Or, for example, a long pulse at a given voltage could be used to “open” the switch, and a short pulse at the same or a similar voltage could be used to “close” the switch. Using these sorts of waveforms may simplify the design of 2-TNS 10 because multiple voltages may not need to be applied to the switch. In particular embodiments of the invention, this phenomenon occurs when currents are limited during program and unrestricted during erase.

It has also been found in some cases that limiting the current that flows through the switch can enhance its ability to switch to the “closed” state. For example, adding a 1 MΩ inline resistor between stimulus circuit 100 and one of conductive element 15 or 20, to limit the current in the switch to less than 1000 nA, can enhance the ability of 2-TNS 10 to switch to the “closed” state by about 40%. Another example is active circuitry that would limit the current during the program cycle. In general, any electrical stimulation that is sufficient to cause 2-TNS 10 to switch to a relatively low-resistance state can be used. In some embodiments, the state is characterized by a resistance R_LOW on the order of about 100 kΩ or less. In some preferred embodiments, the resistance of the relatively high resistance state is at least about 10 times higher than the resistance of the relatively low resistance state. In general, the state can also be considered to be characterized by a relatively low impedance. In some preferred embodiments, the impedance of the relatively high impedance state is at least about 10 times higher than the impedance of the relatively low impedance state.

The two states are nonvolatile, i.e. they do not change until stimulus circuit 100 applies another appropriate electrical stimulus to at least one of conductive elements 15 and 20, and they retain state even if power is removed from the circuit. Stimulus circuit 100 can also determine the state of 2-TNS 10 with a non-destructive read-out operation (NDRO). For example, stimulus circuit 100 applies a low measurement voltage across conductive elements 15 and 20, and measures the resistance, R between the conductive elements. This resistance can be measured by measuring the current flow between conductive elements 15 and 20 and from that calculating the resistance R. The stimulus is sufficiently weak that it does not change the state of the device, for example is a voltage bias of about 1-2 V in some embodiments. In general it is preferable that R_HIGH is at least ten times greater than R_LOW so that stimulus circuit 100 can more easily detect the state.

The inventors believe that when the switch changes states, the conductive pathway in the switch experiences physical changes that modify its ability to carry current. In other words, the inventors believe that the electrical relationship changes between one or more conductors along the conductive pathway due to a change in the physical relationship between the conductors. In the state where the resistance of 2-TNS 10 is high, the inventors believe that an electrical separation, or discontinuity, exists between a sufficient number of conductors to significantly limit the pathway's ability to carry current. This may arise from a physical gap forming between those elements in response to electrical stimulation by stimulus circuit 100. In the state where the resistance of 2-TNS 10 is low, the inventors believe that an electrical contact or continuity exists between a sufficient number of conductors to allow the pathway to carry current relatively well. This may arise from the closing of a gap between one or more conductors in response to electrical stimulation by stimulus circuit 100.

The different conductors in the pathway of the switch include one or more individual nanotubes or nanotube segments in nanotube element 25, and two terminals 15 and 20. Because one or more nanotubes in the nanotube element provide the pathway between the two terminals, it is possible that a change in the physical relationship between the nanotubes and the terminals, and/or between the nanotubes, and/or within or between segments of each individual nanotube itself, causes the change in the switch state. For example, nanotubes may contact one or more of the terminals in the low resistance state, and may lose physical contact with one or more of the terminals in the high resistance state. Or, for example, an electrical network of nanotubes within the nanotube element may touch each other in the low resistance state, and may be separated by gaps in the high resistance state. Or, for example, an individual nanotube may be physically continuous in the low resistance state, and may have a physical gap in the middle of the nanotube in the high resistance state. The two resulting nanotube pieces or segments can each be considered to be a (shorter) nanotube. In general, the physical relationship between a nanotube and one or more conductors in the two-terminal nanotube switch may change. The inventors believe that depending on the particular embodiment, changes in one or more particular kinds of physical relationship, e.g., nanotube to terminal, network nanotube to network nanotube, or intra-nanotube, may predominate the switching behavior of the switch. For different physical design rules of the switch, the phenomena may vary.

The inventors believe that physical changes to the conductive pathway in 2-TNS 10 during an “open” stimulation by stimulus circuit 100 may arise from thermal effects in the conductors. More specifically, the inventors believe that overheating caused by the presence of a threshold voltage and/or current density in at least a portion of the nanotubes of nanotube element 25 may cause the nanotubes in the element to physically separate from one or more conductors in the pathway to form a gap. For example, it has been observed that a threshold current of about 20 microamps can physically break an individual nanotube into two distinct segments, which are separated by a gap. In some embodiments the gap is about 1-2 nm, and in other embodiments the gap is smaller than about 1 nm or larger than about 2 nm. This physical gap prevents current from flowing through the nanotube, yielding an “open” path characterized by a high resistance. If nanotube element 25 is a fabric of nanotubes, then the current in each individual nanotube may generally be a function of the total current and the number or density of nanotubes, accounting for the fact that in some cases many nanotubes may join together to form an electrical pathway. The inventors believe that in some embodiments, by applying a total current sufficient that the current in one or more individual nanotubes exceeds about 20 microamps, those nanotubes may overheat and break. Because those nanotubes no longer carry current, the current in unbroken nanotubes may increase, causing one or more of those nanotubes to overheat and break. Thus in rapid sequence most or all of the current-carrying nanotubes may overheat and break, creating an “open” path or “erased” state in 2-TNS 10, characterized by a relatively high resistance. FIG. 2B is a micrograph of a nanofabric switch that appears to show all or most of the conductive nanotubes pathways broken (for example, see arrow).

Similarly, the inventors believe that overheating caused by a threshold voltage and/or current density applied to the nanotubes may physically break contact between one or more nanotubes within an electrical network of nanotubes. While a particular threshold voltage and/or current density required to separate two nanotubes from each other within 2-TNS 10 is not currently identified, it is possible that the voltage and/or current density is comparable to or lower than that required to break an individual nanotube. Also, overheating caused by a threshold voltage and/or current density may physically break contact between one or more nanotubes in nanotube element 25 and one or more of conductive elements 15 and 20.

The inventors believe that in general, 2-TNS 10 may experience physical breaks at locations susceptible to overheating, e.g., weak thermal links or thermal bottlenecks along the pathway that nanotube element 25 provides between conductive elements 15 and 20. The inventors believe that if the pathway breaks at a given location, the current density may increase throughout the remainder of the pathway, which may induce overheating and breaks at other locations. Thus in rapid sequence most or all of the current-carrying pathways may overheat and break, creating an “open” path or “erased” state in 2-TNS 10, characterized by a relatively high resistance.

The inventors believe that a “close” stimulation by stimulus circuit 100 causes an electrostatic attraction that may cause the creation of a conductive pathway in 2-TNS 10. This attraction may pull or move the nanotubes and conductors into contact with each other. As discussed above, the electrical stimulation that is needed to switch 2-TNS 10 to a “closed” state has been observed to be in part a function of the electrical stimulation that was previously used to switch 2-TNS 10 to an “open” state. The inventors believe that this effect may be related to the size of the gap or gaps that a particular “open” stimulation causes between nanotubes and conductors in the pathway. For example, a relatively low “open” voltage may cause relatively small overheating, which may create relatively small gaps between nanotubes and conductors. Then, a relatively low “close” voltage may be required to sufficiently attract the nanotubes and conductors across those small gaps, and may bring them into contact with each other. Or, for example, a relatively high “open” voltage may cause relatively large overheating, which may create relatively large gaps between nanotubes and conductors. Then, a relatively high “close” voltage may be required to sufficiently attract the nanotubes and conductors across those large gaps, to bring them into contact with each other. An insufficiently high “close” voltage may not attract the nanotubes and conductors with sufficient strength to draw them into contact.

The inventors believe that an undesirably high “close” voltage, for example of about 8-10 V in some embodiments, may be high enough to attract a nanotube to a conductor. However, once the nanotube and conductor touch, the current that begins to flow through the connection may cause a local temperature jump at the connection. This may overheat the connection, and may cause the nanotube and conductor to again separate. This process of connecting and disconnecting may repeat until the “close” voltage is removed. In this case, the switch may fail because it cannot be programmed or “closed.” However, the switch may be closed by a somewhat lower “close” voltage. An undesirably high “open” voltage, for example of about 15-16 V in some embodiments, may cause overheating that may cause a very large gap between the nanotubes and conductors, for example of 30-40 nm. This gap may be so large that no “close” voltage will be high enough to sufficiently attract the nanotubes and conductors so as to bring them into contact with each other. In this case, the switch may fail because it is no longer programmable. The switch may be irreparably damaged because no stimulus is sufficient to attract the nanotubes and conductors into contact.

The inventors believe that an alternative mechanism that can close the electrical pathway by stimulus circuit 100 may be due to electrical arcing that would occur across the gap (a gap formed by a previous “open” operation.) The electrons and/or resulting high temperature may draw material (located in the vicinity of the gap) into the gap, to re-establish a contiguous electrical pathway.

The inventors have observed that if 2-TNS 10 is not passivated, and is stimulated in an inert gas, then the strength of stimulation required to “close” the switch is related to the stimulation used to “open” the switch. In other words, the size of the gap may be related to the “close” stimulation in an inert gas. The inventors have also observed that if 2-TNS 10 is not passivated, and is stimulated in a vacuum, that the strength of the stimulation required to “close” the switch stays approximately constant, within about 10%, regardless of the stimulation used to “open” the switch. In other words, the size of the gap may be unrelated, or weakly related, to the stimulation in a vacuum. The inventors believe that a vacuum may allow heat to build up more rapidly in the nanotube element than it would in a gas, possibly because heat may leak from the nanotube element into the gas.

The inventors believe that overheating caused by the presence of a threshold voltage and/or current in 2-TNS 10, which may break contact between a nanotube and a conductor, is possibly related to the presence of thermally-induced lattice vibrations, or phonons, in the nanotube. In particular, the inventors believe that overheating may excite one or more particular phonon modes in the nanotube, and that this phonon mode may break contact between a nanotube and a conductor. In general, heat excites a spectrum of acoustic and optical phonons in a material, e.g., in a nanotube. Acoustic phonon modes can transport heat, while optical phonon modes generally do not contribute to the transport of heat. Some optical phonon modes may couple to acoustic phonon modes, allowing heat to flow from optical modes into acoustic modes, which then transport heat. However, if heat does not flow easily from optical modes into the acoustic modes, e.g., cannot be transported through the nanotube, then a rapid buildup of heat, or a thermal bottleneck, may occur in the nanotube. This may cause overheating that may be sufficient to break contact between the nanotube and a conductor.

The inventors have obtained Raman spectra for different species of nanotubes that have been tested in 2-TNS 10, and have observed that preferred nanotubes, e.g., nanotubes that consistently exhibit the switching behavior described herein, typically have a pronounced optical phonon mode that corresponds to a radial breathing mode of the nanotube. The inventors believe that this breathing mode may be related to the switching behavior of 2-TNS 10. For example, the mode may behave as a thermal bottleneck, trapping heat inside the nanotube. The mode may allow the nanotube, or a contact between the nanotube and a conductor, to be more easily damaged by a threshold voltage and/or current density than other species of nanotubes that do not exhibit the mode. This breathing mode may also couple to a mode that is related to the breaking of a nanotube, or of contact between the nanotube and a conductor. In other words, the breathing mode itself may not be directly related to the possible formation of gaps in the switch, but may be related to a phenomenon that may form gaps in the switch.

Preferred nanotubes may also have in common other phonon modes that relate to their ability to break contact with conductors. For example, in certain nanotubes one or more defect modes may exist, or one or more modes that may couple strongly to the mode of a bond between the nanotube and a conductor. In general, one or more optical or acoustic phonon modes may contribute to breaking the pathway in 2-TNS 10, e.g., “opening” the switch may be phonon-induced. Different species of nanotubes, for example nanotubes fabricated by different methods or with different process conditions, and/or nanotubes with different numbers of walls, may have different phonon spectra. Some species may possess phonon modes or other features that may cause or enhance the breakability of contact between a nanotube and a conductor. For example, having more than one wall may enhance the breakability of contact between a nanotube and a conductor.

The inventors believe that the switching behavior of 2-TNS 10 may result from a key relationship between the thermal and electrical characteristics of the components of the switch. The inventors believe that two-terminal nanotube switches preferably may provide a sufficiently high voltage and/or current to a nanotube element, and at the same may allow a sufficient amount of heat to build up in the nanotube element so as to break contact between one or more nanotubes and conductors. Preferably, this break is small enough that it can be re-programmably closed. By managing this relationship, preferred embodiments having enhanced performance can be designed and fabricated. These goals may be accomplished with electrical and/or thermal engineering, or management, of the device.

The goal of providing sufficient electrical stimulation to the nanotube element can be accomplished with techniques known in the art. In particular, the conductive elements preferably provide relatively good conduction of current into the nanotube element. The conductive elements are preferably relatively good electrical conductors. For example, the conductive elements can be metal or some other kind of conductive material. Preferably, the conductive elements can be fabricated with processed and materials that are easily integrated into, or already used in, existing fabrication methods. In at least the “closed” state, one or both of the conductive elements is preferably in near-ohmic contact with the nanotube element. Methods of fabricating near-ohmic contacts are known.

The goal of potentially allowing a sufficient amount of heat to build up in the nanotube element so as to break contact between a nanotube and a conductor, in response to an “open” stimulus, is somewhat more challenging. Many materials that can be useful for conductive elements, e.g., that conduct electricity well, also conduct heat well. For example, metals generally conduct electricity well, and are conveniently used in the fabrication of many embodiments of 2-TNS, but typically also conduct heat well. Materials that conduct heat well, e.g., good thermal conductors, may draw enough heat away from the nanotube element that the element may not overheat in response to an “open” stimulation. Alternately, the nanotube element may only overheat in response to an undesirably large “open” stimulation. In order to fabricate a 2-TNS that allows heat to build up in the nanotube element in response to sufficient (but not undesirably large) “open” stimulation, several embodiments of are contemplated.

In some preferred embodiments, the nanotubes themselves may be thermally engineered by selecting them to as to have features that are particularly susceptible to breaking in response to an “open” stimulation. For example, as described above, some nanotubes may be selected to have certain modes that build up heat or couple to other modes that break contact between the nanotube and a conductor. The nanotubes may have defects that are easily broken by overheating. In some embodiments, the nanotubes are pre-treated before deposition in order to induce defects.

In some preferred embodiments, the conductive elements may be thermally engineered by fabricating them from a material (or materials) that conduct electricity relatively well, but conduct heat relatively poorly. For example, the material may have a relatively low thermal conductivity, a relatively high heat capacity, and/or a relatively low thermal diffusion constant. For example, in some embodiments, doped semiconductors may be able to provide a sufficiently high “open” stimulation to the nanotube element, and withdraw a relatively low amount of heat from the nanotube element. Other kinds of materials having this characteristic are contemplated, for example a conductive polymer. Preferably the conductive elements supply a sufficient electrical stimulus to “open” the switch, and at the same time do not significantly impede the buildup of heat in the nanotube element.

Additionally, in some preferred embodiments, the distance between the two conductive elements is relatively small, for example less than about 250 nm. Switches having conductive elements spaced relatively far apart, and therefore have a relatively long nanotube element spanning the distance between them, have been observed to have the tendency to require relatively large “erase” stimuli in order to change the device to an “open” state. Switches with a relatively large spacing between the conductive elements tend to have a higher resistance between the conductive elements, and therefore have a lower current density through the nanotube element for a given erase voltage.

In general, the nanotube element may also be in physical contact with other materials in the 2-TNS besides the conductors, for example an underlying insulator and an overlying passivation layer. These materials may withdraw heat from the nanotube element. In some preferred embodiments, one or more materials that contact the nanotube elements may be selected to be relatively poor thermal conductors, for example having a sufficiently high heat capacity and/or a sufficiently low thermal conductivity. In other words, the materials may transport heat poorly, and may be good thermal insulators. This can be useful because the nanotube element may overheat more readily if materials in contact with the element withdraw little heat from the element. For example, the inventors have found that including a preferred passivation layer over the nanotube element can significantly reduce the level of stimulation required to “open” the 2-TNS, in addition to providing other benefits. By including a preferred passivation layer over the switch, in one embodiment, the stimulation required to “open” the switch was reduced by a factor of two. In general, the inventors believe that it may be preferable that one or more materials that contact the nanotube element preferably conduct heat relatively poorly, which may help heat to build up in the nanotube element.

The inventors believe that preferred passivation layers can also be useful for isolating components of the 2-TNS, e.g., the nanotube element and/or conductive elements, from the environment. For example, water in the air, or that adheres to the nanotube element, can etch the element at high temperatures. If an “open” stimulation is applied to a bare 2-TNS, overheating in the nanotube element may occur at a high enough temperature that any water at the element may sufficiently damage the element so that it no longer conducts current well. This “opens” the 2-TNS, but the switch cannot be subsequently “closed” because the conductive pathway provided by the nanotube element is irreversibly damaged. If instead, the 2-TNS is passivated with a preferred passivation layer, then the switch may be isolated from damaging water and may be repeatedly “opened” and “closed.” It is preferable that any water adhered to the 2-TNS is removed before deposition of the passivation layer; otherwise the layer will simply trap water next to the switch. It is also preferable that the passivation layer does not outgas water, and is not permeable by water. It is also preferable that the passivation layer is not fabricated using a high power plasma, which can damage the nanotube element. Passivation layers may be made from any appropriate material known in the CMOS industry, including, but not limited to: PVDF (Polyvinylidene Fluoride), PSG (Phosphosilicate glass) oxide, Orion oxide, LTO (planarizing low temperature oxide) oxide, sputtered oxide or nitride, flowfill oxide, ALD (atomic layer deposition) oxides. CVD (chemical vapor deposition) nitride also these materials may be used in conjunction with each other, i.e., a PVDF layer or mixture of PVDF and other copolymers may be placed on top of CNTs and this complex may be capped with an ALD Al₂O₃ layer, however any non-oxygen containing high temp polymers could be used as passivation layers. In some preferred embodiments passivation materials such as PVDF may be mixed or formulated with other organic or dielectric materials as copolymers such as PC7 to generate specific passivation properties such as to impart extended lifetime and reliability.

Passivation of NRAM devices may be used to facilitate device operation in air, at room temperature, and as a protecting layer in conjunction with stacked material layers on top on the NRAM device. Operation of unpassivated NRAM devices are typically performed in an inert ambient, such as argon, nitrogen, or helium, or an elevated (greater than 125 C) sample temperature to remove adsorbed water from the exposed nanotubes. Therefore, the requirements of a passivation film are typically twofold. First, the passivation should form an effective moisture barrier, preventing exposure of the nanotubes to water. Second, the passivation film should not interfere with the switching mechanism of the NRAM device.

One approach to passivation involves cavities, which have been fabricated around the NRAM devices to provide a sealed switching region. Cavities both around individual devices (device-level passivation) and around an entire die of 22 devices (die-level passivation) have been demonstrated. However, the process flow to fabricate is complicated, with at least 2 additional lithography steps, and at least 2 additional etching steps required.

Another approach to passivation involves depositing a suitable dielectric layer over the NRAM devices. An example of this approach is the use of spin-coated polyvinyledenefluoride (PVDF) in direct contact with the NRAM devices. The PVDF is patterned into either die-level (over an entire die active region) or device-level patches (individual patches covering individual devices). Then a suitable secondary dielectric passivation film, such an alumina or silicon dioxide is used to seal off the PVDF and provide a passivation robust to NRAM operation. It is thought that NRAM operation thermally decomposes the overlying PVDF, hence a secondary passivation film is required to seal off the devices. Since the die level passivations are typically ˜100 micron square patches, this local decomposition can lead to ruptures of the secondary passivation, exposure of NRAM devices to air, and their subsequent failure. To avoid such failures of the secondary passivation film, the die-level passivated devices are “burned-in” electrically by pulsing the devices typically with 500 ns pulses from 4V to 8V in 0.5V steps. This is thought to controllably decompose the PVDF and prevent a rupture of the overlying secondary passivation film. After the burn-in procedure the die-level passivated NRAM devices operate normally. Devices passivated with a device-level PVDF coating and a secondary passivation film do not require such a burn in procedure and may be operated in air at room temperature directly at operating voltages. With device-level passivation the PVDF is patterned in the exact shape of the CNT fabric, typically 0.5 microns wide and 1-2 microns long. It is thought that such small patches can decompose without stressing the secondary passivation film to failure. It is possible that for a given defect density in the secondary passivation, there are no defects on average over the smaller footprint of the device-level PVDF patches in comparison to the larger, die-level patches.

The inventors believe that in some preferred embodiments, the “open” stimulus applied by the stimulus circuit may be engineered in order to enhance the buildup of heat in the nanotube element. Applying a relatively large voltage to the switch is one example of engineering the “open” stimulus in one embodiment. In other embodiments, a series of pulses may be applied to the switch, and the pulses may be spaced by a timing that is faster than the timescale of the transport of heat out of the nanotube element. The inventors believe that in this case, the pulses themselves do not necessarily have to have a large amplitude, but the total amount of heat deposited in the nanotube element by the pulses may be sufficient to overheat and break the element.

The inventors believe that in some preferred embodiments, two-terminal nanotube switches may be thermally engineered by designing them so as to have a “hot spot,” or thermal bottleneck, where one or more nanotubes may be particularly susceptible to overheating. For example, as described in greater detail below, the nanotube element can be made to partially overlap at least one conductor with a controlled geometrical relationship, e.g., with a controlled overlap length. For example, by controlling the length of overlap to a length that is less than 100 nm, or less than 50 nm, the amount of heat that the conductor can withdraw from the nanotube element may be sufficiently lessened so as to possibly allow rapid overheating of the nanotube element in one or more locations. In contrast, an increased overlap length may inhibit overheating by pulling heat out of the nanotube element.

For example, it has been observed that at least 10% more as-fabricated switches can be “opened” by limiting the overlap length to less than 50 nm, as compared with more than 100 nm. Also, the times required to “open” the switch are significantly reduced for embodiments that have an overlap length of less than 50 nm, which implies or suggests that the nanotube element may overheat more rapidly in response to “open” stimulation. For example, “open” times for as-fabricated switches with less than 50 nm overlap lengths may be on the order of 100 ns, and with greater than 100 nm overlap lengths may be on the order of 1 millisecond or longer. Engineering may provide faster switching speeds, for example as fast as 1 nanosecond or faster. In general, arranging the nanotube element and one or more conductive elements with a specified geometrical relationship may be useful for managing the thermal relationship between the nanotube element and conductive elements. This, or other arrangements, may create a thermal bottleneck, or “hot spot,” in the 2-TNS, that may enhance the operation of the switch.

In summary, in one or more embodiments, thermal and/or electrical engineering, or management, can be used to enhance the performance of a two-terminal nanotube switch. More than one of the described thermal and/or electrical engineering techniques described herein may be used at the same time in the design and fabrication of a preferred two-terminal nanotube switch. For example, a switch can be fabricated having a controlled overlap length to reduce the amount of heat that the conductive element can withdraw from the nanotube element, and the switch can further be passivated with a preferred passivation layer which in some cases may include a mixture of copolymers.

It should be noted that while changes in the resistance of the switch due to electrical stimulation have been repeatedly observed, that the causes of these resistance changes are still being considered from both a theoretical and experimental standpoint. At the time of filing, it is the inventors' belief that thermal effects as described herein may cause or contribute to the observed behavior. Other effects may also cause or contribute the observed behavior.

FIG. 1B illustrates a cross sectional representation of nonvolatile 2-terminal nanotube switch (2-TNS) 10′, in which thermal management is accomplished by limiting the overlap between nanotube element 25′ and conductive element 20′. Nanotube element 25′ is disposed on substrate 35′, which includes a layer of insulator 30′. Nanotube element 25′ is arranged to overlap by a predetermined extent at least a portion of at least one of the terminals, e.g., conductive elements 15′ and 20′, which are both deposited directly onto nanotube element 25′.

In this embodiment, nanotube element 25′ is patterned within a region that can be defined before or after deposition of conductive elements 15′ and/or 20′. Conductive element 15′ overlaps one entire end-region of nanotube element 25′, forming a near-ohmic contact. At the opposite end of nanotube element 25′, at overlap region 45′, conductive element 20′ overlaps nanotube element 25′ by controlled overlap length 40′. Controlled overlap length 40′ may be in the range of 1 to 150 nm, or in the range of 15-50 nm, for example. In one preferred embodiment, controlled overlap length 40′ is about 45 nm. The switch is thermally and electrically managed to enhance the buildup of heat in the nanotube element by limiting the overlap nanotube element 25′ and conductive element 20′ so that heat flows poorly from the nanotube element into the conductive element, with a sufficiently long length of contact that current flows well from the conductive element into the nanotube element.

In one or more embodiments, one or more electrical characteristics of switch 10′ are a function of controlled overlap length 40′. For example, as described in greater detail below, the time required to erase and/or program switch 10′ is a function of controlled overlap length 40′.

FIGS. 2D through 2I show top-view SEM images of a few different embodiments of functional two-terminal nanotube switches, fabricated using the materials, nanotube elements, and methods according to some embodiments described herein. In the embodiment shown in FIG. 2D, 2-TNS 60D is fabricated on a layer of insulator 62D, disposed on a silicon substrate (not visible in this top view). Insulator 62D is about 20 nm of SiO₂, used as a bottom (back) gate. Conductive elements 70D and 75D, which correspond to conductive elements 15′ and 20′ respectively in FIG. 1B, are palladium and have a thickness of about 100 nm. Conductive elements 70D and 75D each have a width of about 400 nm, and have a separation 85D of approximately 150 nm.

In the image, nanotube element 65D includes several nanotubes, which appear in the right half of the image as light grey lines on the grey background of insulator 62D. Conductive element 70D overlaps a substantial portion of nanotube element 65D, resulting in conductive element 70D having a relatively rough texture in the image as compared to the texture of conductive element 75D, which overlaps a limited portion of nanotube element 65C as described in greater detail below. Conductive element 70D has striations such as that indicated by area 55D, which are areas of the element that are raised due to the presence of an underlying nanotube. Nanotube element 65D also can be seen to extend beyond the periphery of conductive element 70D. This feature does not affect the performance of the device, but conveniently allows imaging and/or characterization of an exposed portion of nanotube element 65D.

Some of the nanotubes in nanotube element 65D can be seen to span the distance 85D between conductive elements 70D and 75D. Conductive element 75D overlaps nanotube element 65D in region 80D by a controlled overlap length of about 17.4 nm, which corresponds to controlled overlap length 40′ in FIG. 1B. Conductive elements 70D and 75D can be seen to have white borders, which is a charging artifact of the imaging process. This artifact obscures controlled overlap region 80D, which has a length that is substantially smaller than the length of the artifact. However, as illustrated further below, some embodiments have overlap regions that are large enough to be observed in an SEM micrograph.

The embodiment shown in FIG. 2E has a similar structure to the embodiment of FIG. 2D, with conductive elements 70E and 75E having similar dimensions as the elements in FIG. 2D, but are instead separated by a distance 85E of about 250 nm. The image is rotated by 90 degrees relative to FIG. 2D. Here, conductive element 75E overlaps nanotube element 65E by about 38.6 nm in region 80E. Despite the substantial differences between distances 80D and 80E, and 65D and 65E, the embodiments shown in FIGS. 2D and 2E operate comparably. The embodiment shown in FIG. 2F is similar to the embodiments shown in FIGS. 2D and 2E, but with conductive elements 70F and 75F separated by a distance of about 250 nm. Here, conductive element 75F overlaps nanotube element 65F by about 84.9 nm. The embodiment shown in FIG. 2G is similar to the embodiments shown in FIGS. 2D-2F, but with conductive elements 70G and 75G separated by a distance of about 150 nm. Here, conductive element 75G overlaps nanotube element 65G by about 90.5 nm.

The embodiment shown in FIG. 2G is similar to the embodiments shown in FIGS. 2D-2G, but with conductive elements 70H and 75H separated by a distance of about 150 nm. Here, conductive element 75H overlaps nanotube element 65H by about 104 nm. In this figure, conductive element 75H can be seen to have a significantly roughened texture in region 80H where element 75H overlaps nanotube element 65H. The texture is comparable to that of conductive element 70H, which overlaps a large portion of nanotube element 65H, but region 80H is limited to 104 nm. The embodiment shown in FIG. 2I has a similar structure to that in FIG. 2H, but conductive element 751 overlaps nanotube element 65I in region 80I by about 136 nm. Here conductive element 75I can again be seen to have a significantly roughened texture in region 80I as compared with the rest of the element, which does not overlap nanotube element 65I. This roughened texture results from nanotubes underlying the material of element 75I.

All of the embodiments illustrated in 2D-2I are functional switches, wherein thermal management is accomplished by arranging the nanotube element and a conductive element with a specified geometrical relationship, e.g., a controlled overlap length. In some of the embodiments it was found that the controlled overlap length affected the yield of the as-fabricated working switches, e.g., the percentage of as-fabricated switches of a particular embodiment that functioned properly. For example, it was found that about 10-20% fewer as-fabricated switches of embodiments that had overlap lengths of greater than 100 nm functioned properly, as compared with as-fabricated switches of embodiments that had overlap lengths of less than 50 nm. Methods of testing 2-TNS are described in greater detail below.

The voltages, currents, and resistances listed here are meant to be examples of appropriate values for a particular embodiment; appropriate values may be different for one or more other embodiments.

In certain applications, it may be desirable to overlap the nanotube element with conductive elements in geometries that are different than the embodiments shown in FIG. 1A-1B or 2D-2I in order to thermally engineer the switch. For example, it may be desirable to position the nanotube element above, below, or even on vertical sides of the contact elements. In general any configuration that provides a specified geometry sufficient to allow the described switching behavior in the device can be employed. In particular, the conductive elements should be arranged to provide a sufficient electrical stimulation to the nanotube element, and at the same time the switch as a whole should have sufficient thermal management to allow overheating that breaks contact between a nanotube in the nanotube element and a conductor in the pathway of the switch.

It should be understood that the rest of the embodiments described herein include a stimulus circuit in contact with the conductive elements, e.g., stimulus circuit 100 of FIGS. 1A and 1B, although it is not illustrated. It should also be understood that although many of the described embodiments illustrate two-terminal nanotube switches wherein thermal management is accomplished by limiting the overlap between a nanotube element and a conductive element, e.g., a terminal, other methods of thermal management can be used. For example, in some embodiments the nanotube element can partially or fully overlap one or both conductive elements and the materials in the switch can be selected so as to ensure a sufficient buildup of heat within at least a portion of the nanotube element.

FIG. 3A illustrates switch 900A, which is a variation of 2-TNS 10′ illustrated in FIG. 1B and is fabricated using preferred methods. In this embodiment, conductive element 905 overlaps the top and sides of nanotube element 920, forming a near-ohmic contact, and also fills via hole 910 in insulator 915. This connects nanotube element 920 to an electrode (not shown) below insulator 915. Conductive element 970 overlaps the top and side of nanotube element 920 over controlled overlap length 901.

FIG. 3B illustrates switch 900B, which is another variation of 2-TNS 10′ illustrated in FIG. 1B and is fabricated using preferred methods. In this embodiment, conductive element 935 overlaps the bottom of nanotube element 945, forming a near-ohmic contact, and fills via hole 940 in insulator 915. This connects nanotube element 945 to an electrode (not shown) below insulator 915. Conductive element 975 overlaps the top and side of nanotube element 920 over controlled overlap length 903.

FIG. 3C illustrates switch 900C, which is another variation of 2-TNS 10′ in FIG. 1B and is fabricated using preferred methods. In this embodiment, upper conductive element 950 and lower conductive element 955 in contact with each other, and overlap the top, bottom, and side surfaces of nanotube element 965 forming a near-ohmic contact. Lower contact element 955 fills via hole 960 in insulator 915. This connects nanotube element 965 to an electrode (not shown) below insulator 915. Conductive element 980 overlaps the top and side of nanotube element 965 by controlled overlap length 907.

Upper and lower conductive elements 950 and 955 are illustrated as extending beyond an end of nanotube element 965. Upper and lower conductive elements 950 and 955 are in contact with each other, as well as in near-ohmic contact with nanotube element 965, in the region of nanotube element 965 because nanotube element 965 is porous, typically more than 90% porous. Upper and lower conductive elements 950 and 955 fill at least some of the pores in nanotube element 965. Therefore, in an alternative embodiment, upper and lower conductive elements 950 and 955 need not extend beyond an end of nanotube element 965 to in order to contact nanotube element 965 and each other.

FIG. 3D illustrates switch 900D, which is another variation of 2-TNS 10′ in FIG. 1B and is fabricated using preferred methods. In this embodiment, upper conductive element 950 and lower conductive element 955 in contact with each other, and overlap the top, bottom, and side surfaces of nanotube element 965 forming a near-ohmic contact. Lower contact element 955 fills via hole 960 in insulator 915. This connects nanotube element 965 to an electrode (not shown) below insulator 915. Upper conductive element 980 and lower conductive element 985 in contact with each other, and overlap the top, bottom, and side surfaces of nanotube element 965 by controlled overlap length 907.

FIG. 3E illustrates switch 900E, which is a variation of 2-TNS 10 in FIG. 1A and is fabricated using preferred methods. In this embodiment, upper conductive element 950 and lower conductive element 955 in contact with each other, and overlap the top, and bottom surfaces of nanotube element 965 forming a near-ohmic contact. Material in elements 950 and 955 fill at least some of the pores in nanotube element 965. Lower contact element 955 fills via hole 960 in insulator 915. This connects nanotube element 965 to an electrode (not shown) below insulator 915. Upper conductive element 951 and lower conductive element 956 in contact with each other, and overlap the top and bottom surfaces of nanotube element 965 by controlled overlap length 907. Material in elements 951 and 956 fill at least some of the pores in nanotube element 965. In this embodiment, thermal management is accomplished not by having a controlled overlap length between the nanotube element and a conductive element, but by one or more other thermal management techniques described herein.

FIG. 4 illustrates a cross sectional representation of another embodiment of a nonvolatile two terminal nanotube switch (2-TNS) 2500. In this embodiment, conductive elements 2515 and 2520 are both deposited directly onto the surface of insulator 2530 and patterned. Insulator 2522 fills in regions between patterned conductive elements 2515 and 2520, and is planarized. Nanotube element 2525 is conformally deposited over conductive elements 2515 and 2520, overlapping at least a portion of the top surfaces of conductors 2515 and 2520, as well as the top surface of insulator 2522, all of which are supported by substrate 2535. At one end, nanotube element 2525 overlaps the top surface of conductive element 2515, forming a near-ohmic contact. At an opposing end, nanotube element 2525 contacts the top surface of contact element 2520 by controlled overlap length 2540.

FIG. 5 illustrates a cross sectional representation of another embodiment of a nonvolatile 2-terminal nanotube switch (2-TNS) 2200. In this embodiment, conductive elements 2215 and 2220 are both deposited directly onto the surface of insulator 2230 and patterned. Conductive element 2220 has thickness T1, which may range in thickness from 5 to 500 nm, for example. Nanotube element

1. A two terminal switching device, comprising: a first conductive terminal; a second conductive terminal in spaced relation to the first conductive terminal; a nanotube article having a plurality of nanotubes, said nanotube article being arranged such that the nanotube article is in permanent and direct physical contact with both the first and second conductive terminals; and stimulus circuitry in electrical communication with at least one of the first and second conductive terminals, said stimulus circuitry configured to create a first voltage difference between the first conductive terminal and the second conductive terminal, to induce a change in the resistance of the nanotube article between the first and second conductive terminals from a relatively low resistance to a relatively high resistance, said stimulus circuitry configured to create a second voltage difference between the first conductive terminal and the second conductive terminal, to induce a change in the resistance of the nanotube article between the first and second conductive terminals from a relatively high resistance to a relatively low resistance, wherein the relatively high resistance of the nanotube article between the first and second conductive terminals corresponds to a first state of the two terminal switching device, and wherein the relatively low resistance of the nanotube article between the first and second conductive terminals corresponds to a second state of the two terminal switching device, wherein the first and second states of the two terminal switching device are nonvolatile.

2. The two terminal switching device of claim 1 wherein one or more thermal characteristics of the two terminal switching device are selected to substantially reduce a flow of heat out of the nanotube article.

3. The two terminal switching device of claim 1, wherein the nanotube article permanently overlaps at least a portion of the first conductive terminal with a controlled geometrical relationship.

4. The two terminal switching device of claim 3, wherein the controlled geometrical relationship-is selected to allow electrical current to flow relatively well between the first conductive terminal to the nanotube article, and to allow heat to flow relatively poorly between the first conductive terminal and the nanotube article.

5. The two terminal switching device of claim 3, wherein the controlled geometrical relationship is a predetermined extent of overlap within the range of 1 to 150 nm.

6. The two terminal switching device of claim 3, wherein the controlled geometrical relationship is a predetermined extent of overlap within the range of 15 to 50 nm.

7. The two terminal switching device of claim 4, wherein the controlled geometrical relationship is a predetermined extent of overlap defined by a dimension of the first conductive terminal.

8. The two terminal switching device of claim 1, wherein the first conductive terminal comprises a material that conducts electricity relatively well and conducts heat relatively poorly.

9. The two terminal switching device of claim 1, further comprising a passivation layer disposed on the nanotube article.

10. The two terminal switching device of claim 9, wherein the passivation layer comprises a material that conducts heat relatively poorly.

11. The two terminal switching device of claim 10, wherein the material is selected to substantially trap heat in the nanotube article.

12. The two terminal switching device of claim 1, wherein the resistance of the first state is at least about ten times larger than the resistance of the second state.

13. The two terminal switching device of claim 1, wherein an impedance of the first state is at least about ten times larger than an impedance of the second state.

14. The two terminal switching device of claim 1, wherein the first state is characterized by a resistance above about 1 megaohm.

15. The two terminal switching device of claim 1, wherein the second state is characterized by a resistance below about 100 kilaohm.

16. The two terminal switching device of claim 1, wherein the first voltage difference comprises electrical stimulus selected to provide an erase operation.

17. The two terminal switching device of claim 16, wherein the erase operation comprises the stimulus circuitry applying a relatively high voltage across the first and second terminals.

18. The two terminal switching device of claim 17, wherein the relatively high voltage is within the range of 3 to 10 V.

19. The two terminal switching device of claim 16, wherein the erase operation comprises the stimulus circuitry applying one or more voltage pulses across the first and second terminals, wherein an amplitude of the pulses, a waveform of the pulses, and a number of the pulses together are sufficient to change the two terminal switching device to the first state.

20. The two terminal switching device of claim 1, wherein the second voltage difference comprises electrical stimulus selected to provide a program operation.

21. The two terminal switching device of claim 20, wherein the program operation comprises the stimulus circuitry applying a relatively low voltage and a relatively low current across the first and second conductive terminals.

22. The two terminal switching device of claim 21, wherein the relatively low voltage is within the range of 1 to 5 V and the relatively low current is within the range of 100 nA to 100 uA.

23. The two terminal switching device of claim 20, wherein the program operation comprises the stimulus circuitry applying one or more voltage pulses across the first and second conductive terminals, wherein an amplitude of the pulses, a waveform of the pulses, and a number of the pulses together are sufficient to change the two terminal switching device to the second state.

24. The two terminal switching device of claim 1, wherein the stimulus circuit includes a circuitry configured to create a third voltage difference between the first and second conductive terminals, exclusively, the third waveform having at least one waveform characteristic selected to determine the state of the two terminal switching device.

25. The two terminal switching device of claim 24, wherein the third waveform comprises electrical stimulus selected to provide a non-destructive read-out operation wherein the stimulus circuit applies a voltage across the first and second conductive terminals and senses the resistance between the first and second terminals, the voltage being sufficiently low that it does not change the state of the device.

26. The two terminal switching device of claim 25, wherein the voltage is smaller than about 2 V.

27. The two terminal switching device of claim 1, wherein at least one of the first and second conductive terminals permanently overlaps an edge of the nanotube article.

28. The two terminal switching device of claim 1, wherein opposing ends of the nanotube article respectively permanently overlap at least a portion of each of the first and second conductive terminals.

29. The two terminal switching device of claim 1, wherein one of the first and second conductive terminals is a picture frame structure that permanently overlaps a periphery of the nanotube article, and does not overlap a central region of the nanotube article.

30. The two terminal switching device of claim 29, wherein the other of the first and second conductive terminals permanently overlaps the central region of the nanotube article.

31. The two terminal switching device of claim 1, wherein the first conductive terminal has a plurality of surfaces, wherein the nanotube article substantially conforms to and permanently overlaps at least a portion of more than one of the plurality of surfaces.

32. The two terminal switching device of claim 1, wherein at least one of the first and second conductive terminals has a vertically oriented feature, and wherein the nanotube article substantially conforms to at least a portion of the vertically oriented feature.

33. The two terminal switching device of claim 1, wherein the nanotube article comprises a patterned region of nanotube fabric having a defined orientation and defined dimensions.

34. The two terminal switching device of claim 1, wherein the nanotube article comprises double walled nanotubes.

35. The two terminal switching device of claim 1, wherein the nanotube article comprises single walled nanotubes.

36. The two terminal switching device of claim 1, wherein the nanotube article comprises multiwalled nanotubes.

37. The two terminal switching device of claim 1, wherein the nanotube article comprises bundles of nanotubes.

38. The two terminal switching device of claim 1, wherein one or more nanotubes in the nanotube article are selected to have a particularly strong radial breathing mode.

39. The two terminal switching device of claim 38, wherein the particularly strong radial breathing mode behaves as a thermal bottleneck.

40. The two terminal switching device of claim 38, wherein the particularly strong radial breathing mode couples to a mode that causes a connection between a nanotube and a conductor in the two terminal switching device to break, wherein a conductor in the two terminal switching device comprises one or more of the first conductive terminal, the second conductive terminal, a nanotube, and a nanotube segment.

41. The two terminal switching device of claim 1, wherein the first and conductive second terminals are metal.

42. The two terminal switching device of claim 41, wherein the metal comprises at least one of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiN, TiAu, TiCu, TiPd, PbIn, and TiW.

43. A selectable memory cell, comprising: a cell selection transistor including a gate, a source, and a drain, with the gate in electrical contact with a word line, and a drain in electrical contact with a bit line; a two-terminal switching device comprising a first conductive terminal, a second conductive terminal, and a nanotube article having a plurality of nanotubes, the nanotube article in permanent and direct physical contact with both the first and second conductive terminals, wherein the first conductive terminal is in electrical contact with the source of the memory cell selection transistor and the second conductive terminal is in electrical contact with a program/erase/read line; and a memory operation circuit in electrical communication with the word line, bit line, and program/erase/read line, said memory operation circuit including circuitry configured to generate and apply a select signal on the word line to select the memory cell and for generating and for applying an erase signal on the program/erase/read line, the erase signal creating a voltage difference between the first conductive terminal and the second conductive terminal and selected to induce a change in the resistance of the nanotube article between the first and second conductive terminals from a relatively low resistance to a relatively high resistance, said memory operation circuit including circuitry configured to generate and apply a select signal on the word line to select the memory cell and for generating and for applying a program signal on the program/erase/read line, the program signal creating a voltage difference between the first conductive terminal and the second conductive terminal and selected to induce a change in the resistance of the nanotube article between the first and second conductive terminals from a relatively high resistance to a relatively low resistance, wherein the relatively high resistance of the nanotube article between the first and second conductive terminals corresponds to a first informational state of the memory cell, and wherein the relatively high resistance of the nanotube article between the first and second conductive terminals corresponds to a second informational state of the memory cell, wherein the first and second informational states are nonvolatile.

44. The selectable memory cell of claim 43, wherein said memory operation circuit includes circuitry for generating and for applying a select signal on the word line to select the cell and for generating and for applying a read signal on the program/erase/read line, wherein the read signal has at least one waveform characteristic selected to determine the informational state of the memory cell.

45. The selectable memory cell of claim 44, wherein determining the informational state of the memory cell does not change the informational state of the memory cell.

46. The selectable memory cell of claim 43, further comprising a plurality of selectable memory cells connected to the program/erase/read line.

47. The selectable memory cell of claim 43, wherein one or more thermal characteristics of the device are selected to substantially reduce a flow of heat out of the nanotube article.

48. The selectable memory cell of claim 43, wherein the nanotube article permanently overlaps at least a portion of the second conductive terminal with a controlled geometrical relationship.

49. The selectable memory cell of claim 48, wherein the controlled geometrical relationship allows electrical current to flow relatively well between the second conductive terminal and the nanotube article, and allows heat to flow relatively poorly between the second conductive terminal and the nanotube article.

50. The selectable memory cell of claim 48, wherein the controlled geometrical relationship comprises a predetermined extent of overlap defined by a dimension of the first conductive terminal.

51. The selectable memory cell of claim 48, wherein the controlled geometrical relationship comprises a predetermined extent of overlap within the range of 1 to 150 nm.

52. The selectable memory cell of claim 43, wherein one of the first and second conductive terminals is a picture frame structure that permanently overlaps a periphery of the nanotube article, and does not overlap the central region of the nanotube article, and wherein the other of the first and second conductive terminals permanently overlaps a central region of the nanotube article.

53. The selectable memory cell of claim 43, wherein the second conductive terminal has a plurality of surfaces, and wherein the nanotube article substantially conforms to and permanently overlaps at least a portion of more than one surface.

54. The selectable memory cell of claim 43, wherein the second conductive terminal has a vertically oriented feature, and wherein the nanotube article substantially conforms to at least a portion of the vertically oriented figure.

55. The selectable memory cell of claim 43, wherein the nanotube article comprises a patterned region of nanotube fabric having a defined orientation and defined dimensions.

56. The selectable memory cell of claim 43, wherein the nanotube article comprises double walled nanotubes.

57. The selectable memory cell of claim 43, wherein the nanotube article comprises multiwalled nanotubes.

58. The selectable memory cell of claim 43, wherein the nanotube article comprises bundles of nanotubes.

59. The selectable memory cell of claim 43, wherein the first and second conductive terminals are metal.