Micron Technology

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No	Document	Title	Date
101	US 2012/0008404 A1 patent application	System and method for reducing pin-count of memory devices, and memory device testers for same Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data...	12-Jan-2012
102	US 2012/0008440 A1 patent application	Data retention kill function Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or...	12-Jan-2012
103	US 2012/0009779 A1 patent application	Contact formation The present disclosure includes various methods of contact embodiments. One such method embodiment includes forming a trench in an insulator stack material of a particular thickness. This method includes...	12-Jan-2012
104	US 2012/0009793 A1 patent application	Method for selectively modifying spacing between pitch multiplied structures Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and...	12-Jan-2012
105	US 2012/0007037 A1 patent application	Cross-point memory utilizing ru/Si diode Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further...	12-Jan-2012
106	US 2012/0009776 A1 patent application	Semiconductor substrates with unitary vias and via terminals, and associated systems and methods Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in...	12-Jan-2012
107	US 2012/0011335 A1 patent application	Memory controllers, memory systems, solid state drives and methods for processing a number of commands The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively...	12-Jan-2012
108	US 8093643 B2 patent document	Multi-resistive integrated circuit memory A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the...	10-Jan-2012
109	US 8093937 B2 patent document	Seamless coarse and fine delay structure for high performance DLL A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and fine delays. The system may use a single coarse...	10-Jan-2012
110	US 8093666 B2 patent document	Lanthanide yttrium aluminum oxide dielectric films Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium...	10-Jan-2012
111	US 8093730 B2 patent document	Underfilled semiconductor die assemblies and methods of forming the same An apparatus and method may be used for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide a robust, inflexible cost-effective bond. The...	10-Jan-2012
112	US 8095765 B2 patent document	Memory block management Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two...	10-Jan-2012
113	US 8093638 B2 patent document	Systems with a gate dielectric having multiple lanthanide oxide layers Electronic systems and methods of forming the electronic systems include a gate dielectric having multiple lanthanide oxide layers. Such electronic systems may be used in a variety of electronic system...	10-Jan-2012
114	US 8093129 B2 patent document	Methods of forming memory cells Some embodiments include methods of forming memory cells. A semiconductor construction may be provided, with such construction including tunnel dielectric material over a semiconductor substrate. The...	10-Jan-2012
115	US 8093725 B2 patent document	High aspect ratio contacts A contact formed in accordance with a process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating layer to a second plasma of a second...	10-Jan-2012
116	US 8094045 B2 patent document	Data bus inversion apparatus, systems, and methods Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms....	10-Jan-2012
117	US 8095835 B2 patent document	Error scanning in flash memory Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more...	10-Jan-2012
118	US 8093155 B2 patent document	Method of controlling striations and CD loss in contact oxide etch A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low...	10-Jan-2012
119	US 8093658 B2 patent document	Electronic device with asymmetric gate strain The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode...	10-Jan-2012
120	US 8093702 B2 patent document	Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a...	10-Jan-2012
121	US 8095748 B2 patent document	Method and apparatus for sending data from multiple sources over a communications bus In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and...	10-Jan-2012
122	US 8094047 B2 patent document	Data serializer apparatus and methods Some embodiments include apparatus and methods having an output line, clock nodes to receive clock signals, the clock signals being out of phase with each other, and selector circuits to receive data in...	10-Jan-2012
123	US 8093090 B1 patent document	Integrated circuit edge and method to fabricate the same In the fabrication of an integrated circuit, a trench with a sidewall is formed along the periphery of the integrated circuit and the substrate is back-lapped to a thickness smaller than the trench depth to...	10-Jan-2012
124	US 8094507 B2 patent document	Command latency systems and methods Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced...	10-Jan-2012
125	US 8095834 B2 patent document	Macro and command execution from memory array Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions...	10-Jan-2012
126	US 8093576 B1 patent document	Chemical-mechanical polish termination layer to build electrical device isolation A method of forming a semiconductor device may comprise forming a memory portion, forming a carbon film, depositing insulation to at least partially cover the carbon film, and terminating patterned removal of...	10-Jan-2012
127	US 8094508 B2 patent document	Memory block testing A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than...	10-Jan-2012
128	US 8094984 B2 patent document	Semiconductor constructions, methods of forming semiconductor constructions, light-conducting conduits, and optical signal propagation assemblies The invention includes optical signal conduits having rare earth elements incorporated therein. The optical signal conduits can, for example, contain rare earth elements incorporated within a dielectric...	10-Jan-2012
129	US 2012/0002468 A1 patent application	Cell deterioration warning apparatus and method Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices...	05-Jan-2012
130	US 2012/0003810 A1 patent application	Semiconductor device having reduced sub-threshold leakage A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is...	05-Jan-2012
131	US 2012/0001147 A1 patent application	Non-Volatile Resistive Oxide Memory Cells, Non-Volatile Resistive Oxide Memory Arrays, And Methods Of Forming Non-Volatile Resistive Oxide Memory Cells And Memory Arrays A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode....	05-Jan-2012
132	US 2012/0001248 A1 patent application	Methods of forming nanoscale floating gate A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and...	05-Jan-2012
133	US 2012/0001680 A1 patent application	Isolation circuit The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor configured for connection to a supply...	05-Jan-2012
134	US 2012/0001253 A1 patent application	Flatband voltage adjustment in a semiconductor device Memory devices, methods for fabricating, and methods for adjusting flatband voltages are disclosed. In one such memory device, a pair of source/drain regions are formed in a semiconductor. A dielectric material...	05-Jan-2012
135	US 2012/0001682 A1 patent application	Apparatuses and methods to reduce power consumption in digital circuits An apparatus and method for reducing power consumption in digital circuits, particularly circuits including a charge pump. A driver may selectively drive a signal line, such as a memory device wordline, between...	05-Jan-2012
136	US 2012/0002465 A1 patent application	Methods, structures, and devices for reducing operational energy in phase change memory Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some...	05-Jan-2012
137	US 2012/0005411 A1 patent application	Non-volatile configuration for serial non-volatile memory Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to...	05-Jan-2012
138	US 2012/0001144 A1 patent application	Resistive ram devices and methods The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a...	05-Jan-2012
139	US 2012/0001299 A1 patent application	Semiconductor Constructions Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of...	05-Jan-2012
140	US 2012/0001245 A1 patent application	Recessed Access Device for a Memory Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that...	05-Jan-2012
141	US 2012/0001539 A1 patent application	Plasma-Generating Structures, Display Devices, and Methods of Forming Plasma-Generating Structures Some embodiments include methods of forming plasma-generating microstructures. Aluminum may be anodized to form an aluminum oxide body having a plurality of openings extending therethrough. Conductive liners...	05-Jan-2012
142	US 2012/0002477 A1 patent application	Memories and their formation Memories and their formation are disclosed. One such memory has first and second memory cells at a first vertical level of the memory, first and second memory cells at a second vertical level of the memory, a...	05-Jan-2012
143	US 2012/0003573 A1 patent application	Photomasks Some embodiments include methods of forming photomasks. A stack of at least three different materials is formed over a base. Regions of the stack are removed to leave a mask pattern over the base. The mask...	05-Jan-2012
144	US 2012/0001246 A1 patent application	Memory device and method of fabricating thereof Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device.	05-Jan-2012
145	US 2012/0002467 A1 patent application	Single transistor memory cell A semiconductor device along with circuits including same and methods of operating same are disclosed. In one particular embodiment, the device may comprise a memory cell including a transistor. The transistor...	05-Jan-2012
146	US 2012/0002489 A1 patent application	Signal driver circuit having adjustable output voltage for a high logic level output signal A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a...	05-Jan-2012
147	US 8088659 B2 patent document	Method of forming capacitors High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in...	03-Jan-2012
148	US 8089805 B2 patent document	Two-part programming methods and memories Programming a memory in two parts to reduce cell disturb includes, in at least one embodiment, programming data in two or more sequences of programming pulses with data requiring higher programming voltages...	03-Jan-2012
149	US 8089816 B2 patent document	Memory erase methods and devices Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining...	03-Jan-2012
150	US 8090955 B2 patent document	Boot block features in synchronous serial interface NAND Embodiments are provided for protecting boot block space in a NAND memory device connected to a host device via an SPI interface. One such method includes programming a boot block password into the NAND memory...	03-Jan-2012
151	US 8088551 B2 patent document	Methods of utilizing block copolymer to form patterns Some embodiments include methods of forming patterns in which a block copolymer-containing composition is formed over a substrate, and is then patterned to form a first mask. The block copolymer of the...	03-Jan-2012
152	US 8088643 B2 patent document	Resistance variable memory device with nanoparticle electrode and method of fabrication A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the...	03-Jan-2012
153	US 8089123 B2 patent document	Semiconductor device comprising transistor structures and methods for forming same A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded...	03-Jan-2012
154	US 8088691 B2 patent document	Selective etch chemistries for forming high aspect ratio features and associated structures An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an...	03-Jan-2012
155	US 8089128 B2 patent document	Transistor gate forming methods and integrated circuits A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate...	03-Jan-2012
156	US 8089800 B2 patent document	Memory cell Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory...	03-Jan-2012
157	US 8090886 B2 patent document	Direct secondary device interface by a host A device has a controller and a function module configured to be in communication with the controller as a result of the controller receiving a pass-through vendor specific command. In some embodiments the...	03-Jan-2012
158	US 8089142 B2 patent document	Methods and apparatus for a stacked-die interposer An improved stacked-die package includes an interposer which improves the manufacturability of the package. A semiconductor package includes a package substrate having a plurality of bond pads; a first...	03-Jan-2012
159	US 8089387 B2 patent document	Quantizing circuits with variable parameters Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing...	03-Jan-2012
160	US 8088293 B2 patent document	Methods of forming reticles configured for imprint lithography The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into...	03-Jan-2012
161	US 8089542 B2 patent document	CMOS imager with integrated circuitry A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. Integrating a CMOS imager and peripheral...	03-Jan-2012
162	US 8090999 B2 patent document	Memory media characterization for development of signal processors Methods and apparatus utilizing media characterization of memory devices facilitate the development of signal processors for analyzing memory device outputs. Models are developed from capturing output of memory...	03-Jan-2012
163	US 2011/0316726 A1 patent application	Low power multi-level signaling Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal...	29-Dec-2011
164	US 2011/0315944 A1 patent application	Resistive memory and methods of processing resistive memory Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an...	29-Dec-2011
165	US 2011/0316114 A1 patent application	Simplified pitch doubling process flow A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality...	29-Dec-2011
166	US 2011/0316125 A1 patent application	Intermediate structures for forming circuits In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a...	29-Dec-2011
167	US 2011/0317509 A1 patent application	Memory device word line drivers and methods Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors...	29-Dec-2011
168	US 2011/0318899 A1 patent application	Methods of Forming Capacitors Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more...	29-Dec-2011
169	US 2011/0318921 A1 patent application	Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact...	29-Dec-2011
170	US 2011/0317473 A1 patent application	System and method for mitigating reverse bias leakage The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the...	29-Dec-2011
171	US 2011/0316042 A1 patent application	Thyristor random access memory device and method Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for...	29-Dec-2011
172	US 2011/0316091 A1 patent application	Semiconductor Devices, Assemblies And Constructions Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material....	29-Dec-2011
173	US 2011/0316512 A1 patent application	Voltage trimming Embodiments are provided that include a memory die, memory devices, and methods, such as those comprising a voltage generator, including an output voltage and an adjustment circuit configured to cause...	29-Dec-2011
174	US 2011/0317502 A1 patent application	Control of inputs to a memory device A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface...	29-Dec-2011
175	US 2011/0315543 A1 patent application	Forming memory using high power impulse magnetron sputtering Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron...	29-Dec-2011
176	US 2011/0316599 A1 patent application	Multi-phase clock generation An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock...	29-Dec-2011
177	US 2011/0317046 A1 patent application	Missing pixel array An active pixel sensor (APS) comprises a regular repeating pattern of geometrically similar pixel regions, active pixels of which have photodiodes formed therein. A remainder of the geometrically similar...	29-Dec-2011
178	US 2011/0316068 A1 patent application	Flash memory with recessed floating gate A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device...	29-Dec-2011
179	US 8084142 B2 patent document	Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a...	27-Dec-2011
180	US 8084296 B2 patent document	Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a first support member, a second support member,...	27-Dec-2011
181	US 8084843 B2 patent document	N well implants to separate blocks in a flash memory device A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated...	27-Dec-2011
182	US 8084854 B2 patent document	Pass-through 3D interconnect for microelectronic dies and associated systems and methods Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first...	27-Dec-2011
183	US 8085594 B2 patent document	Reading technique for memory cell with electrically floating body transistor A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor...	27-Dec-2011
184	US 8085584 B1 patent document	Memory to store user-configurable data polarity Subject matter disclosed herein relates to user configuration of polarity of data storage in memory devices.	27-Dec-2011
185	US 8085612 B2 patent document	Method and apparatus for managing behavior of memory devices A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a...	27-Dec-2011
186	US 8084345 B2 patent document	Methods of forming dispersions of nanoparticles, and methods of forming flash memory cells Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the nanoparticles are coordinated to hydrophobic ligands,...	27-Dec-2011
187	US 8084370 B2 patent document	Hafnium tantalum oxynitride dielectric Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more...	27-Dec-2011
188	US 8084846 B2 patent document	Balanced semiconductor device packages including lead frame with floating leads and associated methods A semiconductor device assembly or package includes at least one semiconductor device that is positioned adjacent to floating leads. Such an assembly or package may include at least two semiconductor devices...	27-Dec-2011
189	US 8085591 B2 patent document	Charge loss compensation during programming of a memory device In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory...	27-Dec-2011
190	US 8084322 B2 patent document	Method of manufacturing devices having vertical junction edge Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide...	27-Dec-2011
191	US 8084355 B2 patent document	Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry A method of forming copper-comprising conductive lines in the fabrication of integrated circuitry includes depositing damascene material over a substrate. Line trenches are formed into the damascene material....	27-Dec-2011
192	US 8085606 B2 patent document	Input-output line sense amplifier having adjustable output drive capability An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage...	27-Dec-2011
193	US 8086790 B2 patent document	Non-volatile memory device having assignable network identification Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each...	27-Dec-2011
194	US 8086916 B2 patent document	System and method for running test and redundancy analysis in parallel A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions...	27-Dec-2011
195	US 8084845 B2 patent document	Subresolution silicon features and methods for forming the same Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic...	27-Dec-2011
196	US 8085596 B2 patent document	Reducing noise in semiconductor devices The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor...	27-Dec-2011
197	US 8086913 B2 patent document	Methods, apparatus, and systems to repair memory Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address...	27-Dec-2011
198	US 8086920 B2 patent document	Method of controlling a test mode of a circuit A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode...	27-Dec-2011
199	US 8083953 B2 patent document	Registered structure formation via the application of directed thermal energy to diblock copolymer films Methods for fabricating sublithographic, nanoscale linear microchannel arrays over surfaces without defined features utilizing self-assembling block copolymers, and films and devices formed from these methods...	27-Dec-2011
200	US 8084806 B2 patent document	Isolation structure for a memory cell using A12O3 dielectric The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated circuit structure,...	27-Dec-2011

Showing 101-200 of 26967 results

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