Micron Technology

Showing 201-300 of 26967 results

<<	<	Page:	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	>	>>

No	Document	Title	Date
201	US 8084808 B2 patent document	Zirconium silicon oxide films Electronic apparatus and systems include structures having a dielectric layer containing a zirconium silicon oxide film. A zirconium silicon oxide film may be disposed in an integrated circuit, as well as in a...	27-Dec-2011
202	US 8084866 B2 patent document	Microelectronic devices and methods for filling vias in microelectronic devices Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature...	27-Dec-2011
203	US 2011/0310687 A1 patent application	Current sense amplifiers, memory devices and methods A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that...	22-Dec-2011
204	US 2011/0309393 A1 patent application	Packaged leds with phosphor films, and associated systems and methods Packaged LEDs with phosphor films, and associated systems and methods are disclosed. A system in accordance with a particular embodiment of the disclosure includes a support member having a support member bond...	22-Dec-2011
205	US 2011/0314215 A1 patent application	Multi-priority encoder A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a...	22-Dec-2011
206	US 2011/0309319 A1 patent application	Horizontally oriented and vertically stacked memory cells Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on...	22-Dec-2011
207	US 2011/0309506 A1 patent application	Conductive interconnect structures and formation methods using supercritical fluids Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via...	22-Dec-2011
208	US 2011/0310661 A1 patent application	Memory sensing devices, methods, and systems The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating...	22-Dec-2011
209	US 2011/0310683 A1 patent application	Non-volatile memory control Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are...	22-Dec-2011
210	US 2011/0310679 A1 patent application	Devices, systems, and methods for a power generator system Methods, devices, and systems are provided for a power generator system. The power generator system may include a control device configured to output a first reference voltage and a second reference voltage...	22-Dec-2011
211	US 2011/0309324 A1 patent application	Solid state devices with semi-polar facets and associated methods of manufacturing Solid state lighting devices with semi-polar or non-polar surfaces and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material...	22-Dec-2011
212	US 2011/0310689 A1 patent application	Power source and power source control circuit Power sources, backup power circuits, power source control circuits, data storage devices, and methods relating to controlling application of power to a node are disclosed. An example power source includes an...	22-Dec-2011
213	US 2011/0310675 A1 patent application	Local sensing in a memory device Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides...	22-Dec-2011
214	US 8082382 B2 patent document	Memory device with user configurable density/performance The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of storing a selectable quantity of data bits (e.g.,...	20-Dec-2011
215	US 8082456 B2 patent document	Data controlled power supply apparatus A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power...	20-Dec-2011
216	US 8080837 B2 patent document	Memory devices, transistors, and memory cells A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do...	20-Dec-2011
217	US 8081511 B2 patent document	Flash memory device with redundant columns Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a...	20-Dec-2011
218	US 8082435 B2 patent document	Memory device initiate and terminate boot commands Memory devices and methods facilitate initiation and termination of boot data output from a memory device through the use of received commands. For example, boot data output is initiated in response to a...	20-Dec-2011
219	US 8080816 B2 patent document	Silver-selenide/chalcogenide glass stack for resistance variable memory The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a...	20-Dec-2011
220	US 8082387 B2 patent document	Methods, systems, and devices for management of a memory system Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with the architecture of...	20-Dec-2011
221	US 8082404 B2 patent document	Memory arbitration system and method having an arbitration packet protocol A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative...	20-Dec-2011
222	US 8080460 B2 patent document	Methods of forming diodes Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material,...	20-Dec-2011
223	US 8080817 B2 patent document	Memory cells In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the...	20-Dec-2011
224	US 8081249 B2 patent document	Image sensor with a gated storage node linked to transfer gate A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer gate and provides a storage node for a pixel,...	20-Dec-2011
225	US 8081020 B2 patent document	Delay-lock loop and method adapting itself to operate over a wide frequency range A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a...	20-Dec-2011
226	US 8080615 B2 patent document	Crosslinkable graft polymer non-preferentially wetted by polystyrene and polyethylene oxide Methods for fabricating a random graft PS-r-PEO copolymer and its use as a neutral wetting layer in the fabrication of sublithographic, nanoscale arrays of elements including openings and linear microchannels...	20-Dec-2011
227	US 8082413 B2 patent document	Detection circuit for mixed asynchronous and synchronous memory operation A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit receives the memory address signals, the control...	20-Dec-2011
228	US 2011/0303929 A1 patent application	Multi-dimensional led array system and associated methods and structures A formed, multi-dimensional light-emitting diode (LED) array is disclosed. A substrate is bent into a trapezoidal shape having different sections facing in different directions. Each section has one or more...	15-Dec-2011
229	US 2011/0307682 A1 patent application	Block management for mass storage An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory being organized into blocks with each block...	15-Dec-2011
230	US 2011/0304358 A1 patent application	Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of...	15-Dec-2011
231	US 2011/0305021 A1 patent application	Solid state lighting device with different illumination parameters at different regions of an emitter array Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a plurality of SSL emitters carried by the support....	15-Dec-2011
232	US 2011/0305090 A1 patent application	Memory controller self-calibration for removing systemic influence Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the...	15-Dec-2011
233	US 2011/0303957 A1 patent application	Concentric or Nested Container Capacitor Structure for Integrated Circuits Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one...	15-Dec-2011
234	US 8076200 B2 patent document	Charge trapping dielectric structures with variable band-gaps A nonvolatile read-only memory having a thin nitrided tunnel insulator surface with a charge blocking insulator over the nitrided surface is presented. The tunnel insulator may be formed of a metal oxide, a...	13-Dec-2011
235	US 8076208 B2 patent document	Method for forming transistor with high breakdown voltage using pitch multiplication technique Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material separated by shallow trench isolaton structures. The...	13-Dec-2011
236	US 8076211 B2 patent document	Fabricating bipolar junction select transistors for semiconductor memories A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed...	13-Dec-2011
237	US 8076244 B2 patent document	Methods for causing fluid to flow through or into via holes, vents and other openings or recesses that communicate with surfaces of substrates of semiconductor device components A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to...	13-Dec-2011
238	US 8076673 B2 patent document	Recessed gate dielectric antifuse A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide...	13-Dec-2011
239	US 8076714 B2 patent document	Memory device with high dielectric constant gate dielectrics and metal floating gates A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The...	13-Dec-2011
240	US 8078796 B2 patent document	Method for writing to and erasing a non-volatile memory A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write operations for the non-volatile memory, each write...	13-Dec-2011
241	US 8078848 B2 patent document	Memory controller having front end and back end channels for modifying commands The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command...	13-Dec-2011
242	US 8076229 B2 patent document	Methods of forming data cells and connections to data cells Disclosed are methods and devices, among which is a method that includes forming a lower conductive material on a substrate, forming a stop material on the substrate, forming a sacrificial material on the...	13-Dec-2011
243	US 8076760 B2 patent document	Semiconductor fuse arrangements The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts...	13-Dec-2011
244	US 8077532 B2 patent document	Small unit internal verify read in a memory device Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory block). Mask...	13-Dec-2011
245	US 8078797 B2 patent document	Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices A memory storage system of an embodiment includes a nonvolatile memory unit and memory control circuitry coupled to the memory unit. Storage locations of the memory unit are organized into one or more...	13-Dec-2011
246	US 8077515 B2 patent document	Methods, devices, and systems for dealing with threshold voltage change in memory devices The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having...	13-Dec-2011
247	US 8077519 B2 patent document	Programming a memory device to increase data reliability Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of...	13-Dec-2011
248	US 8076717 B2 patent document	Vertically-oriented semiconductor selection device for cross-point array memory A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more...	13-Dec-2011
249	US 8078001 B2 patent document	Methods, apparatuses and systems for piecewise generation of pixel correction values for image processing Methods, apparatuses and systems providing pixel correction values for a captured image, where the correction values are determined based on a piecewise-quadratic correction function in a first direction. The...	13-Dec-2011
250	US 8076248 B2 patent document	Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative to conductive material The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal...	13-Dec-2011
251	US 8076721 B2 patent document	Fin structures and methods of fabricating fin structures There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein...	13-Dec-2011
252	US 8076195 B2 patent document	Resistive memory architectures with multiple memory cells per access device A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent...	13-Dec-2011
253	US 8076249 B2 patent document	Structures containing titanium silicon oxide A dielectric containing a titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments...	13-Dec-2011
254	US 8078018 B2 patent document	Communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses Some embodiments include communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses. In one embodiment, a communication method...	13-Dec-2011
255	US 8076727 B2 patent document	Magnesium-doped zinc oxide structures and methods Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently...	13-Dec-2011
256	US 8074353 B2 patent document	Methods of providing semiconductor components within sockets The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets. The sockets can be configured so that compression...	13-Dec-2011
257	US 8076663 B2 patent document	Phase change memory structures Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change...	13-Dec-2011
258	US 8077538 B2 patent document	Address decoder and/or access line driver and method for memory devices Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC damage and avoids GIDL currents in transistors in...	13-Dec-2011
259	US 2011/0300721 A1 patent application	Methods of Making Crystalline Tantalum Pentoxide There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating...	08-Dec-2011
260	US 2011/0300689 A1 patent application	Methods of Forming Trench Isolation in the Fabrication of Integrated Circuitry and Methods of Fabricating Integrated Circuitry First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that...	08-Dec-2011
261	US 2011/0301383 A1 patent application	Beta-Diketiminate Ligand Sources and Metal-Containing Compounds Thereof, and Systems and Methods Including Same The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In certain embodiments, the metal-containing compounds...	08-Dec-2011
262	US 2011/0298014 A1 patent application	Cross-Point Memory Structures Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device...	08-Dec-2011
263	US 2011/0298512 A1 patent application	Circuit, system and method for controlling read latency A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output...	08-Dec-2011
264	US 2011/0300782 A1 patent application	Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces are disclosed herein. In one embodiment, an end effector for conditioning a polishing pad includes a member...	08-Dec-2011
265	US 2011/0298007 A1 patent application	Select devices including an open volume, memory devices and systems including same, and methods for forming same Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced...	08-Dec-2011
266	US 2011/0298494 A1 patent application	Methods, devices, and systems for a high voltage tolerant buffer Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry that provide voltages to thin-gate dielectric transistors. One such buffer may include a primary pull-up...	08-Dec-2011
267	US 2011/0302470 A1 patent application	Test mode for parallel load of address dependent data to enable loading of desired data backgrounds One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and costs associated with testing. A background data...	08-Dec-2011
268	US 2011/0297927 A1 patent application	Oxide based memory Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a...	08-Dec-2011
269	US 2011/0298504 A1 patent application	Clock generator and methods using closed loop duty cycle correction Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators...	08-Dec-2011
270	US 2011/0299329 A1 patent application	Bottom electrode geometry for phase change memory A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom...	08-Dec-2011
271	US 8071467 B2 patent document	Methods of forming patterns, and methods of forming integrated circuits Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly may be formed over a substrate, with the assembly...	06-Dec-2011
272	US 8072523 B2 patent document	Redundancy in column parallel or row architectures A column circuitry architecture for an imager includes redundant column or row circuits. The column or row circuitry includes a number of redundant column or row circuits. Each column or row circuit include...	06-Dec-2011
273	US 8072820 B2 patent document	System and method for reducing pin-count of memory devices, and memory device testers for same Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data...	06-Dec-2011
274	US 8073890 B2 patent document	Continuous high-frequency event filter A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a...	06-Dec-2011
275	US 8073986 B2 patent document	Memory devices configured to identify an operating mode Memory devices having a memory module, an interface, identification circuitry and a controller coupled to the memory module and the identification circuitry. The identification circuitry is configured to...	06-Dec-2011
276	US 8072054 B2 patent document	Lead frame A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a...	06-Dec-2011
277	US 8072249 B2 patent document	Clock jitter compensated clock circuits and methods for generating jitter compensated clock signals Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive a reference clock signal and generate an output...	06-Dec-2011
278	US 8072055 B2 patent document	High density stacked die assemblies, structures incorporated therein and methods of fabricating the assemblies A stacked semiconductor die assembly includes at least two partially offset semiconductor dice with bond pads located adjacent at least one peripheral side thereof supported on a redistribution element formed...	06-Dec-2011
279	US 8072504 B2 patent document	Method and system for aiding user alignment for capturing partially overlapping digital images A method and system for aiding user alignment of two or more partially overlapping digital images. A first image is captured. A portion of a first image is displayed with a preview of a portion of a second...	06-Dec-2011
280	US 8072836 B2 patent document	Systems, methods and devices for arbitrating die stack position in a multi-die stack device Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked dies are arbitrated to select one of the dies as...	06-Dec-2011
281	US 8071416 B2 patent document	Method of forming a uniform color filter array A method of forming a uniform color filter array. In one embodiment, a first compensation layer is formed over a non-planar color filter array and is patterned to form material structures. A second compensation...	06-Dec-2011
282	US 8071441 B2 patent document	Methods of forming DRAM arrays Some embodiments include methods of forming transistor gates. A gate stack is placed within a reaction chamber and subjected to at least two etches, and to one or more depositions to form a transistor gate. The...	06-Dec-2011
283	US 8072082 B2 patent document	Pre-encapsulated cavity interposer A pre-encapsulated cavity interposer, a pre-encapsulated frame, for a semiconductor device.	06-Dec-2011
284	US 8072520 B2 patent document	Dual pinned diode pixel with shutter A pixel having an electronic shutter suitable for use in a pixel array of an imaging device includes a pinned diode and a shutter transistor. The pinned diode is utilized as a storage device while the shutter...	06-Dec-2011
285	US 8072812 B2 patent document	Sensing of memory cells in NAND flash An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a...	06-Dec-2011
286	US 8072814 B2 patent document	NAND with back biased operation Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve...	06-Dec-2011
287	US 8074159 B2 patent document	Method and apparatus for detecting communication errors on a bus A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The...	06-Dec-2011
288	US 8071443 B2 patent document	Method of forming lutetium and lanthanum dielectric structures Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide....	06-Dec-2011
289	US 8071476 B2 patent document	Cobalt titanium oxide dielectric films Electronic apparatus and methods of forming the electronic apparatus include a cobalt titanium oxide film on a substrate for use in a variety of electronic systems. The cobalt titanium oxide film may be...	06-Dec-2011
290	US 8072037 B2 patent document	Method and system for electrically coupling a chip to chip package A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the...	06-Dec-2011
291	US 8071262 B2 patent document	Reticles with subdivided blocking regions An attenuated phase shift reticle, or photomask, includes radiation blocking regions that are subdivided, by cut lines, into discrete, spaced apart sections with dimensions (e.g., surface area, etc.) that are...	06-Dec-2011
292	US 8071480 B2 patent document	Method and apparatuses for removing polysilicon from semiconductor workpieces Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface...	06-Dec-2011
293	US 8072816 B2 patent document	Memory block reallocation in a flash memory device A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the...	06-Dec-2011
294	US 8072838 B2 patent document	Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock synchronization circuit and tracking and recording the control...	06-Dec-2011
295	US 8074122 B2 patent document	Program failure recovery A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the memory device to a first location of a memory of the...	06-Dec-2011
296	US 2011/0296093 A1 patent application	Program and sense operations in a non-volatile memory device Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same...	01-Dec-2011
297	US 2011/0291224 A1 patent application	Efficient pitch multiplication process Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a...	01-Dec-2011
298	US 2011/0296144 A1 patent application	Reducing data hazards in pipelined processors to provide high processor utilization A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple...	01-Dec-2011
299	US 2011/0296077 A1 patent application	Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least...	01-Dec-2011
300	US 2011/0294294 A1 patent application	Protective coating for planarization Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced...	01-Dec-2011

Showing 201-300 of 26967 results

<<	<	Page:	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	>	>>