Micron Technology

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No	Document	Title	Date
401	US 8055816 B2 patent document	Memory controllers, memory systems, solid state drives and methods for processing a number of commands The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively...	08-Nov-2011
402	US 8053909 B2 patent document	Semiconductor component having through wire interconnect with compressed bump A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the...	08-Nov-2011
403	US 2011/0266610 A1 patent application	Memory devices having reduced interference between floating gates and methods of fabricating such devices A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region...	03-Nov-2011
404	US 2011/0267362 A1 patent application	Gamma variation using illumination intensity A gamma variation of image intensity is created by varying the illumination intensity during a pulse width modulated display time period. During the pulse width modulated display time period a ramp signal may...	03-Nov-2011
405	US 2011/0269252 A1 patent application	Method for positioning spacers for pitch multiplication Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and...	03-Nov-2011
406	US 2011/0269288 A1 patent application	Methods of Forming CoSi2, Methods of Forming Field Effect Transistors, and Methods of Forming Conductive Contacts The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a...	03-Nov-2011
407	US 2011/0266696 A1 patent application	Semiconductor device packages including a semiconductor device and a redistribution element A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets...	03-Nov-2011
408	US 2011/0266647 A1 patent application	Methods of Forming Isolated Active Areas, Trenches, and Conductive Lines in Semiconductor Structures and Semiconductor Structures Including the Same Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for...	03-Nov-2011
409	US 2011/0266694 A1 patent application	Methods of manufacturing semiconductor structures and devices including nanotubes, and semiconductor structures, devices, and systems fabricated using such methods A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally...	03-Nov-2011
410	US 2011/0267882 A1 patent application	Memory array with inverted data-lines pairs At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second...	03-Nov-2011
411	US 2011/0267912 A1 patent application	Digit line equilibration using access devices at the edge of sub arrays A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a...	03-Nov-2011
412	US 2011/0266701 A1 patent application	Novel build-up package for integrated circuit devices, and methods of making same A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that...	03-Nov-2011
413	US 2011/0271158 A1 patent application	Method and apparatus for testing high capacity/High bandwidth memory devices A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit...	03-Nov-2011
414	US 2011/0266689 A1 patent application	Methods Of Forming A Plurality Of Conductive Lines In The Fabrication Of Integrated Circuitry, Methods Of Forming An Array Of Conductive Lines, And Integrated Circuitry A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the...	03-Nov-2011
415	US 2011/0271038 A1 patent application	Indexed register access for memory device Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device....	03-Nov-2011
416	US 8048755 B2 patent document	Resistive memory and methods of processing resistive memory Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an...	01-Nov-2011
417	US 8049514 B2 patent document	Integrated circuit inspection system Methods and systems that include a nanotube used as an emitter in the testing and fabrication of integrated circuits. The nanotube emits a signal to a substrate. Based on the signal or the electrical...	01-Nov-2011
418	US 8048708 B2 patent document	Method and apparatus providing an imager module with a permanent carrier Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer.	01-Nov-2011
419	US 8049298 B2 patent document	Isolation trenches for memory devices A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the...	01-Nov-2011
420	US 8049331 B2 patent document	Structure and method for forming a capacitively coupled chip-to-chip signaling interface A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second...	01-Nov-2011
421	US 8049791 B2 patent document	Method, apparatus and system using hierarchical histogram for automatic exposure adjustment of an image An automatic exposure control circuit and a method for generating a hierarchical histogram for exposure control. The control circuit and the method result in the generation of a histogram with sub-histograms of...	01-Nov-2011
422	US 8050096 B2 patent document	Programming method to reduce gate coupling interference for non-volatile memory A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by...	01-Nov-2011
423	US 8051358 B2 patent document	Error recovery storage along a nand-flash string Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental...	01-Nov-2011
424	US 8049258 B2 patent document	Disposable pillars for contact formation Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to...	01-Nov-2011
425	US 8050102 B2 patent document	Word line activation in memory devices Memory devices and methods facilitate flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one...	01-Nov-2011
426	US 8049200 B2 patent document	Bottom electrode for memory device and method of forming the same Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in...	01-Nov-2011
427	US 8048756 B2 patent document	Method for removing metal layers formed outside an aperture of a BPSG layer utilizing multiple etching processes including electrochemical-mechanical polishing A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate...	01-Nov-2011
428	US 8050090 B2 patent document	Memory page boosting method, device and system A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells...	01-Nov-2011
429	US 2011/0261624 A1 patent application	Data line management in a memory device Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods...	27-Oct-2011
430	US 2011/0260778 A1 patent application	Semiconductor Temperature Sensor Using Bandgap Generator Circuit A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive...	27-Oct-2011
431	US 2011/0263135 A1 patent application	Semiconductor Processing Methods, And Methods For Forming Silicon Dioxide Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate may have an inner region and an outer region...	27-Oct-2011
432	US 2011/0260298 A1 patent application	Semiconductor structures including square cuts in single crystal silicon and method of forming same A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts...	27-Oct-2011
433	US 2011/0260236 A1 patent application	Transistor Constructions and Processing Methods A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region...	27-Oct-2011
434	US 2011/0261607 A1 patent application	Arrays Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells, Methods Of Forming Arrays Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells, And Methods Of Reading A Data Value Stored By An Array Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally...	27-Oct-2011
435	US 8045040 B2 patent document	Correction of non-uniform sensitivity in an image array An improved non-uniform sensitivity correction algorithm for use in an imager device (e.g., a CMOS APS). The algorithm provides zones having flexible boundaries which can be reconfigured depending upon the type...	25-Oct-2011
436	US 8045356 B2 patent document	Memory modules having daisy chain wiring configurations and filters Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which...	25-Oct-2011
437	US 8043911 B2 patent document	Methods of forming semiconductor constructions The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath...	25-Oct-2011
438	US 8043915 B2 patent document	Pitch multiplied mask patterns for isolated features Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of...	25-Oct-2011
439	US 8043975 B2 patent document	Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition...	25-Oct-2011
440	US 8043964 B2 patent document	Method for providing electrical connections to spaced conductive lines An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads...	25-Oct-2011
441	US 8044479 B2 patent document	Transistors, semiconductor devices, assemblies and constructions Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material....	25-Oct-2011
442	US 8045386 B2 patent document	Methods and apparatus for programming a memory cell using one or more blocking memory cells Methods and apparatus for programming a memory cell using one or more blocking memory cells facilitate mitigation of capacitive voltage coupling. The methods include applying a program voltage to a selected...	25-Oct-2011
443	US 8045395 B2 patent document	Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias...	25-Oct-2011
444	US 8046646 B2 patent document	Defective memory block identification in a memory device During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free...	25-Oct-2011
445	US 8045416 B2 patent document	Method and memory device providing reduced quantity of interconnections Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus...	25-Oct-2011
446	US 8043961 B2 patent document	Method of forming a bond pad A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive...	25-Oct-2011
447	US 8046542 B2 patent document	Fault-tolerant non-volatile integrated circuit memory Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate...	25-Oct-2011
448	US 8043944 B2 patent document	Process for enhancing solubility and reaction rates in supercritical fluids Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films...	25-Oct-2011
449	US 8046628 B2 patent document	Failure recovery memory devices and methods Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an...	25-Oct-2011
450	US 2011/0256644 A1 patent application	Masks for microlithography and methods of making and using such masks Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one...	20-Oct-2011
451	US 2011/0254627 A1 patent application	Signaling systems, preamplifiers, memory devices and methods Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a...	20-Oct-2011
452	US 2011/0256711 A1 patent application	Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a...	20-Oct-2011
453	US 2011/0256706 A1 patent application	Method of forming a semiconductor structure A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention...	20-Oct-2011
454	US 2011/0258425 A1 patent application	Boot partitions in memory devices and systems The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot...	20-Oct-2011
455	US 2011/0254075 A1 patent application	Use of dilute steam ambient for improvement of flash devices A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween....	20-Oct-2011
456	US 2011/0254067 A1 patent application	DRAM Layout with Vertical FETS and Method of Formation DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are...	20-Oct-2011
457	US 2011/0254144 A1 patent application	Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member and at...	20-Oct-2011
458	US 2011/0254129 A1 patent application	Electrical components for microelectronic devices and methods of forming the same Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming...	20-Oct-2011
459	US 2011/0255342 A1 patent application	Memory voltage cycle adjustment The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a...	20-Oct-2011
460	US 2011/0253042 A1 patent application	Methods of Processing Semiconductor Substrates, Electrostatic Carriers for Retaining Substrates for Processing, and Assemblies Comprising Electrostatic Carriers Having Substrates Electrostatically Bonded Thereto A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier....	20-Oct-2011
461	US 2011/0255343 A1 patent application	Programming in a memory device Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming...	20-Oct-2011
462	US 2011/0256694 A1 patent application	Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-On-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic...	20-Oct-2011
463	US 2011/0258360 A1 patent application	Methods and Systems to Accomplish Variable Width Data Input Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and...	20-Oct-2011
464	US 2011/0252623 A1 patent application	Microelectronic devices and microelectronic support devices, and associated assemblies and methods Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a microelectronic device that includes a...	20-Oct-2011
465	US 2011/0253965 A1 patent application	Vertical transistor phase change memory Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor,...	20-Oct-2011
466	US 2011/0255341 A1 patent application	Programming methods for a memory device Methods for programming, memory devices, and memory systems are disclosed. In one such method for programming, a target memory cell is partially programmed to a final target programmed state where the partial...	20-Oct-2011
467	US 2011/0254163 A1 patent application	Sleeve insulators and semiconductor device including the same A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve...	20-Oct-2011
468	US 2011/0254604 A1 patent application	Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is...	20-Oct-2011
469	US 2011/0255344 A1 patent application	Charge loss compensation during programming of a memory device A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the...	20-Oct-2011
470	US 2011/0254072 A1 patent application	Charge storage structures and methods Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a...	20-Oct-2011
471	US 8039287 B2 patent document	Method of forming high gain, low noise, photodiode sensor for image sensors Embodiments of the present invention provide a pixel cell for an image sensor that includes a photodiode, which provides high gain, low noise, and low dark current. The pixel cell includes a photodiode...	18-Oct-2011
472	US 8039881 B2 patent document	Deuterated structures for image sensors and methods for forming the same A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device.	18-Oct-2011
473	US 8042012 B2 patent document	Systems and devices including memory with built-in self test and methods of making and using the same Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. The quantizing...	18-Oct-2011
474	US 8039882 B2 patent document	High gain, low noise photodiode for image sensors and method of formation Embodiments of the present invention provide a pixel cell for an image sensor that includes a photodiode, which provides high gain, low noise, and low dark current. The pixel cell includes a photodiode...	18-Oct-2011
475	US 8040732 B2 patent document	NAND memory device column charging Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns...	18-Oct-2011
476	US 8042022 B2 patent document	Method, system, and apparatus for distributed decoding during prolonged refresh Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be...	18-Oct-2011
477	US 8039300 B2 patent document	Reproducible resistance variable insulating memory devices and methods for forming same The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the thickness of the insulating material at the tip of the...	18-Oct-2011
478	US 8039377 B2 patent document	Semiconductor constructions Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of...	18-Oct-2011
479	US 8039340 B2 patent document	Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced...	18-Oct-2011
480	US 8039399 B2 patent document	Methods of forming patterns utilizing lithography and spacers Some embodiments include methods of forming patterns. A first set of features is photolithographically formed over a substrate, and then a second set of features is photolithographically formed over the...	18-Oct-2011
481	US 8039357 B2 patent document	Integrated circuitry and methods of forming a semiconductor-on-insulator substrate Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic...	18-Oct-2011
482	US 8039348 B2 patent document	Vertical gated access transistor According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At...	18-Oct-2011
483	US 8040753 B2 patent document	System and method for capturing data signals using a data strobe signal A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal....	18-Oct-2011
484	US 8039327 B2 patent document	Transistor forming methods A transistor forming method includes forming a dielectric spacer in a trench surrounding an active area island, forming line openings through the spacer, and forming a gate line extending through the line...	18-Oct-2011
485	US 2011/0247561 A1 patent application	Thermal Chemical Vapor Deposition Methods, and Thermal Chemical Vapor Deposition Systems One embodiment thermal chemical vapor deposition method includes exposing a substrate within a chamber to first and second deposition precursors effective to thermally chemical vapor deposit a material on the...	13-Oct-2011
486	US 2011/0249488 A1 patent application	Data Cells with Drivers and Methods of Making and Operating the Same Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate,...	13-Oct-2011
487	US 2011/0249503 A1 patent application	Select gate programming in a memory device Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines....	13-Oct-2011
488	US 2011/0248752 A1 patent application	Clock signal generators having a reduced power feedback clock path and methods for generating clocks Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal,...	13-Oct-2011
489	US 2011/0249494 A1 patent application	Multiple select gates with non-volatile memory cells Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices,...	13-Oct-2011
490	US 2011/0250753 A1 patent application	Atomic Layer Deposition Methods An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective...	13-Oct-2011
491	US 2011/0250759 A1 patent application	Method to Reduce Charge Buildup During High Aspect Ratio Contact Etch A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A...	13-Oct-2011
492	US 2011/0249499 A1 patent application	Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments...	13-Oct-2011
493	US 2011/0249507 A1 patent application	Sensing memory cells The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an...	13-Oct-2011
494	US 2011/0248778 A1 patent application	Devices comprising colossal magnetocapacitive materials and related methods Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The gate structure is configured to affect electrical...	13-Oct-2011
495	US 2011/0248385 A1 patent application	Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during fabrication of a semiconductor device and electronic systems including the semiconductor device A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask,...	13-Oct-2011
496	US 8034716 B2 patent document	Semiconductor structures including vertical diode structures and methods for making the same Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and...	11-Oct-2011
497	US 8033884 B2 patent document	Methods of forming plasma-generating structures; methods of plasma-assisted etching, and methods of plasma-assisted deposition Some embodiments include methods of forming plasma-generating microstructures. Aluminum may be anodized to form an aluminum oxide body having a plurality of openings extending therethrough. Conductive liners...	11-Oct-2011
498	US 8034706 B2 patent document	Contact formation The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a particular thickness and having a portion of the...	11-Oct-2011
499	US 8034728 B2 patent document	Systems and methods for forming metal oxides using metal diketonates and/or ketoimines A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more precursor...	11-Oct-2011
500	US 8035433 B2 patent document	Process insensitive delay line A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to...	11-Oct-2011

Showing 401-500 of 26967 results

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