Micron Technology

Showing 501-600 of 26967 results

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No	Document	Title	Date
501	US 8035160 B2 patent document	Recessed access device for a memory Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that...	11-Oct-2011
502	US 8034315 B2 patent document	Methods of forming devices comprising carbon nanotubes Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest...	11-Oct-2011
503	US 8034702 B2 patent document	Methods of forming through substrate interconnects A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line...	11-Oct-2011
504	US 8036058 B2 patent document	Symmetrically operating single-ended input buffer devices and methods Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied...	11-Oct-2011
505	US 8037378 B2 patent document	Automatic test entry termination in a memory device A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key or command as the next command received, the test...	11-Oct-2011
506	US 8036035 B2 patent document	Erase cycle counter usage in a memory device Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such...	11-Oct-2011
507	US 8035129 B2 patent document	Integrated circuitry This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises...	11-Oct-2011
508	US 8035189 B2 patent document	Semiconductor constructions The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam...	11-Oct-2011
509	US 8037381 B2 patent document	Error detection, documentation, and correction in a flash memory device A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array....	11-Oct-2011
510	US 8034516 B2 patent document	Photomasks, methods of forming photomasks, and methods of photolithographically-patterning substrates Some embodiments include methods of forming photomasks. A stack of at least three different materials is formed over a base. Regions of the stack are removed to leave a mask pattern over the base. The mask...	11-Oct-2011
511	US 8034655 B2 patent document	Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode....	11-Oct-2011
512	US 8035142 B2 patent document	Deuterated structures for image sensors and methods for forming the same A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device.	11-Oct-2011
513	US 8036019 B2 patent document	Resistive memory The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least...	11-Oct-2011
514	US 8036334 B2 patent document	Delay lock loop phase glitch error filter A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a...	11-Oct-2011
515	US 8035179 B2 patent document	Packaged microelectronic imagers and methods of packaging microelectronic imagers Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one...	11-Oct-2011
516	US 8034687 B2 patent document	Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width...	11-Oct-2011
517	US 8036016 B2 patent document	Maintenance process to enhance memory endurance Subject matter disclosed herein relates to enhancing an operational lifespan of non-volatile memory.	11-Oct-2011
518	US 8037446 B2 patent document	Methods for defining evaluation points for optical proximity correction and optical proximity correction methods including same Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation points for use in optical proximity correction of...	11-Oct-2011
519	US 2011/0242878 A1 patent application	Methods for operating memory elements Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements,...	06-Oct-2011
520	US 2011/0241205 A1 patent application	Semiconductor with through-substrate interconnect Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is...	06-Oct-2011
521	US 2011/0241041 A1 patent application	Light emitting diode thermally enhanced cavity package and method of manufacture Several embodiments of light emitting diode packaging configurations including a substrate with a cavity are disclosed herein. In one embodiment, a cavity is formed on a substrate to contain an LED and phosphor...	06-Oct-2011
522	US 2011/0241096 A1 patent application	Isolation regions Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate...	06-Oct-2011
523	US 2011/0244404 A1 patent application	Photoresist Processing Methods A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes...	06-Oct-2011
524	US 2011/0242915 A1 patent application	Method and apparatus for reducing oscillation in synchronous circuits Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An...	06-Oct-2011
525	US 2011/0242900 A1 patent application	Memory cell sensing devices and methods The present disclosure includes methods, devices, and systems for sensing memory cells. One or more embodiments include providing an output of a first counter to a digital-to-analog converter (DAC). An output...	06-Oct-2011
526	US 2011/0240596 A1 patent application	Methods Using Block Co-Polymer Self-Assembly for Sub-Lithographic Patterning Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock copolymers, triblock copolymers, multiblock...	06-Oct-2011
527	US 2011/0242901 A1 patent application	Lifetime markers for memory devices The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses...	06-Oct-2011
528	US 2011/0242925 A1 patent application	Reduction of fusible links and associated circuitry on memory dies The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial...	06-Oct-2011
529	US 8030217 B2 patent document	Simplified pitch doubling process flow A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality...	04-Oct-2011
530	US 8030780 B2 patent document	Semiconductor substrates with unitary vias and via terminals, and associated systems and methods Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in...	04-Oct-2011
531	US 8032694 B2 patent document	Direct logical block addressing flash memory mass storage architecture A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is...	04-Oct-2011
532	US 8030156 B2 patent document	Methods of forming DRAM arrays Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more...	04-Oct-2011
533	US 8030952 B2 patent document	Power sink for IC temperature control The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC...	04-Oct-2011
534	US 8030170 B2 patent document	Methods of forming isolation structures, and methods of forming nonvolatile memory Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A...	04-Oct-2011
535	US 8032804 B2 patent document	Systems and methods for monitoring a memory system Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters...	04-Oct-2011
536	US 8031529 B2 patent document	Memory cell threshold voltage drift estimation methods and apparatus Methods of operating memory devices include determining a threshold voltage drift of two or more reference memory cells of the memory device programmed to only a subset of data states of the memory device and,...	04-Oct-2011
537	US 8031518 B2 patent document	Methods, structures, and devices for reducing operational energy in phase change memory Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some...	04-Oct-2011
538	US 8030748 B2 patent document	Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side,...	04-Oct-2011
539	US 8032350 B2 patent document	Techniques for generating and simulating a simulatable vector having amplitude noise and/or timing jitter added thereto Methods for generating realistic waveform vectors with controllable amplitude noise and timing jitter, simulatable in a computer-based simulation environment are disclosed. In one implementation, a transition...	04-Oct-2011
540	US 8030168 B2 patent document	Methods of forming DRAM memory cells The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact...	04-Oct-2011
541	US 8030751 B2 patent document	Board-on-chip type substrates with conductive traces in multiple planes and semiconductor device packages including such substrates A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets...	04-Oct-2011
542	US 8029947 B2 patent document	Systems and methods for implementing and manufacturing reticles for use in photolithography tools Methods, systems, and tool sets involving reticles and photolithography processing. Several embodiments of the invention are directed toward obtaining qualitative data from within the pattern area of a reticle...	04-Oct-2011
543	US 8030211 B2 patent document	Methods for forming bit line contacts and bit lines during the formation of a semiconductor device A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases processing latitude, particularly the spacing...	04-Oct-2011
544	US 8031249 B2 patent document	Missing pixel architecture An active pixel sensor (APS) comprises a regular repeating pattern of geometrically similar pixel regions, active pixels of which have photodiodes formed therein. A remainder of the geometrically similar...	04-Oct-2011
545	US 8032778 B2 patent document	Clock distribution apparatus, systems, and methods Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional...	04-Oct-2011
546	US 8029858 B2 patent document	Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a substrate The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first species monolayer is chemisorbed onto a substrate...	04-Oct-2011
547	US 8030218 B2 patent document	Method for selectively modifying spacing between pitch multiplied structures Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and...	04-Oct-2011
548	US 8030636 B2 patent document	Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first,...	04-Oct-2011
549	US 2011/0235450 A1 patent application	Current mode sense amplifier with passive load Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to...	29-Sep-2011
550	US 2011/0237081 A1 patent application	Methods of Forming Memory; and Methods of Forming Vertical Structures Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from...	29-Sep-2011
551	US 2011/0239061 A1 patent application	Systems and methods for retrieving data Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating...	29-Sep-2011
552	US 2011/0236568 A1 patent application	Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer...	29-Sep-2011
553	US 2011/0233581 A1 patent application	Solid state lighting devices with cellular arrays and associated methods of manufacturing Solid state lighting (“SSL”) devices with cellular arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode includes a semiconductor material having a first...	29-Sep-2011
554	US 2011/0233705 A1 patent application	Wafer processing Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces substantially...	29-Sep-2011
555	US 2011/0239093 A1 patent application	Fault-tolerant non-volatile integrated circuit memory Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate...	29-Sep-2011
556	US 2011/0235306 A1 patent application	Multi-lens solid state lighting devices Solid state lighting (SSL) devices including a plurality of SSL emitters and methods for manufacturing SSL devices are disclosed. Several embodiments of SSL devices in accordance with the technology include a...	29-Sep-2011
557	US 2011/0233740 A1 patent application	Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a...	29-Sep-2011
558	US 2011/0233734 A1 patent application	Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-On-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic...	29-Sep-2011
559	US 2011/0237042 A1 patent application	Methods Utilizing Microwave Radiation During Formation Of Semiconductor Constructions Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some...	29-Sep-2011
560	US 2011/0233745 A1 patent application	Integrated Circuit Packages Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive...	29-Sep-2011
561	US 2011/0235455 A1 patent application	Voltage regulators, amplifiers, memory devices and methods Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path...	29-Sep-2011
562	US 2011/0235418 A1 patent application	Determining memory page status The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using...	29-Sep-2011
563	US 2011/0232515 A1 patent application	Methods of forming a stamp, a stamp and a patterning system A method of patterning a substrate is disclosed. An ink material is chemisorbed to at least one region of a stamp and the chemisorbed ink material is transferred to a receptor substrate. The ink material has...	29-Sep-2011
564	US 2011/0233671 A1 patent application	Threshold voltage adjustment of a transistor A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and...	29-Sep-2011
565	US 2011/0235433 A1 patent application	Verifying an erase threshold in a memory device In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase...	29-Sep-2011
566	US 2011/0235422 A1 patent application	Apparatus having a string of memory cells Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have...	29-Sep-2011
567	US 2011/0233641 A1 patent application	Non-volatile memory cell devices and methods A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the...	29-Sep-2011
568	US 2011/0234257 A1 patent application	Output driver robust to data dependent noise Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a...	29-Sep-2011
569	US 2011/0237029 A1 patent application	Circuit and method for interconnecting stacked integrated circuit dies Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through...	29-Sep-2011
570	US 2011/0233777 A1 patent application	Through-wafer interconnects for photoimager and memory wafers A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable...	29-Sep-2011
571	US 2011/0233686 A1 patent application	Interconnecting bit lines in memory devices for multiplexing An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the...	29-Sep-2011
572	US 2011/0234324 A1 patent application	System and method for reducing lock time in a phase-locked loop Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop...	29-Sep-2011
573	US 2011/0233774 A1 patent application	Electronic devices formed of two or more substrates connected together, electronic systems comprising electronic devices, and methods of forming electronic devices Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at least substantially parallel to each other through at...	29-Sep-2011
574	US 8026579 B2 patent document	Silicon pillars for vertical transistors In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a...	27-Sep-2011
575	US 8027187 B2 patent document	Memory sensing devices, methods, and systems The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating...	27-Sep-2011
576	US 8026501 B2 patent document	Method of removing or deposting material on a surface including material selected to decorate a particle on the surface for imaging A method that may be applied to imaging and identifying defects and contamination on the surface of an integrated circuit is described. An energetic beam, such as an electron beam, may be directed at a selected...	27-Sep-2011
577	US 8026148 B2 patent document	Methods of utilizing silicon dioxide-containing masking structures Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the...	27-Sep-2011
578	US 8026180 B2 patent document	Methods of modifying oxide spacers Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided. Embodiments of the methods can be used for spacer or line...	27-Sep-2011
579	US 8026966 B2 patent document	Method, apparatus and system providing a storage gate pixel with high dynamic range A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which charges are accumulated in a photosensor and repeatedly...	27-Sep-2011
580	US 8026747 B2 patent document	Apparatus and method for multi-phase clock generation An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock...	27-Sep-2011
581	US 8026967 B2 patent document	Rolling shutter for prevention of blooming A rolling shutter technique for a pixel array is described in which multiple rows of the array are hard reset as the shutter moves down the array. As the rolling shutter progresses down the array, each row is...	27-Sep-2011
582	US 8026542 B2 patent document	Low resistance peripheral local interconnect contacts with selective wet strip of titanium Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.	27-Sep-2011
583	US 8026740 B2 patent document	Multi-level signaling for low power, short channel applications Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal...	27-Sep-2011
584	US 8025809 B2 patent document	Polishing methods A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a portion of the abrasive material, and removing at least...	27-Sep-2011
585	US 8026161 B2 patent document	Highly reliable amorphous high-K gate oxide ZrO2 A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a...	27-Sep-2011
586	US 8026750 B2 patent document	Delay locked loop circuit and method Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a...	27-Sep-2011
587	US 8026702 B2 patent document	Voltage regulator system The present disclosure includes circuits, systems and methods for regulating voltage. One voltage regulator system embodiment includes a voltage regulator having an output and a number of stages coupled in...	27-Sep-2011
588	US 8027200 B2 patent document	Reduction of quick charge loss effect in a memory device Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to...	27-Sep-2011
589	US 8028198 B2 patent document	Devices, methods, and apparatuses for detection, sensing, and reporting functionality for semiconductor memory Methods, apparatuses and systems are disclosed for a memory device. In one embodiment, a memory device is disclosed that may include a command error module operably coupled to a mode register, a command input,...	27-Sep-2011
590	US 2011/0229804 A1 patent application	Microlithography masks including image reversal assist features, microlithography systems including such masks, and methods of forming such masks Microlithography masks are disclosed, such as those that include one or more image reversal assist features disposed between at least two primary mask features. The one or more image reversal assist features...	22-Sep-2011
591	US 2011/0227108 A1 patent application	Light emitting diodes with enhanced thermal sinking and associated methods of operation Solid state lighting devices and associated methods of thermal sinking are described below. In one embodiment, a light emitting diode (LED) device includes a heat sink, an LED die thermally coupled to the heat...	22-Sep-2011
592	US 2011/0228617 A1 patent application	Techniques for reducing a voltage swing Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic...	22-Sep-2011
593	US 2011/0228607 A1 patent application	Adjusting program and erase voltages in a memory device A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first...	22-Sep-2011
594	US 2011/0227106 A1 patent application	Light emitting diodes and methods for manufacturing light emitting diodes Light emitting diodes and methods for manufacturing light emitting diodes are disclosed herein. In one embodiment, a method for manufacturing a light emitting diode (LED) comprises applying a first light...	22-Sep-2011
595	US 2011/0231143 A1 patent application	System and method for controlling timing of output signals The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a...	22-Sep-2011
596	US 2011/0227142 A1 patent application	Fortification of charge-storing material in high-k dielectric environments and resulting appratuses Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the...	22-Sep-2011
597	US 2011/0230007 A1 patent application	Semiconductor fabrication method and system A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method includes attaching a carrier to a substrate including a via to form a pressurized sealed cavity between the carrier...	22-Sep-2011
598	US 2011/0226589 A1 patent application	Mechanic extractor of dry grains stored in silage bag with discharge accelerator An extracting machine has a transverse roll that rolls a silage bag up as grains stored therein are extracted, to be discharged to a hopper truck. An extracting head placed in the interior of the bag has a...	22-Sep-2011
599	US 2011/0227887 A1 patent application	Adjustment of liquid crystal display voltage Drive voltages of a liquid crystal display are adjusted based on one or more environmental conditions. The pixel drive voltages may be adjusted based on temperature. A pixel voltage may be varied such that it...	22-Sep-2011
600	US 2011/0230033 A1 patent application	Fabrication of finned memory arrays Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched...	22-Sep-2011

Showing 501-600 of 26967 results

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