Micron Technology

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No	Document	Title	Date
1	US 2012/0026792 A1 patent application	Erase cycle counter usage in a memory device Memory devices to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle...	02-Feb-2012
2	US 2012/0030452 A1 patent application	Modifying commands The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command...	02-Feb-2012
3	US 2012/0025402 A1 patent application	Methods of forming semiconductor device structures and semiconductor device structures including a uniform pattern of conductive lines Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In...	02-Feb-2012
4	US 2012/0028410 A1 patent application	Methods of forming germanium-antimony-tellurium materials and a method of forming a semiconductor device structure including the same A method of forming a material. The method comprises conducting an ALD layer cycle of a first metal, the ALD layer cycle comprising a reactive first metal precursor and a co-reactive first metal precursor. An...	02-Feb-2012
5	US 2012/0026816 A1 patent application	Defective memory block identification in a memory device During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free...	02-Feb-2012
6	US 2012/0030529 A1 patent application	Refresh of non-volatile memory cells based on fatigue conditions In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells...	02-Feb-2012
7	US 2012/0030545 A1 patent application	Error recovery storage along a nand-flash string Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental...	02-Feb-2012
8	US 2012/0030638 A1 patent application	Methods for defining evaluation points for optical proximity correction and optical proximity correction methods including same Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation points for use in optical proximity correction of...	02-Feb-2012
9	US 8107344 B2 patent document	Phase masks for use in holographic data storage A spatial light modulator (SLM) having a phase mask that is provided as an internal component thereof. The phase mask can be provided as a multilevel surface of relatively higher index of refraction material on...	31-Jan-2012
10	US 8106438 B2 patent document	Stud capacitor device and fabrication method The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in the substrate, depositing a first conductive layer...	31-Jan-2012
11	US 8106520 B2 patent document	Signal delivery in stacked device Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one...	31-Jan-2012
12	US 8106491 B2 patent document	Methods of forming stacked semiconductor devices with a leadframe and associated assemblies A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of...	31-Jan-2012
13	US 8107218 B2 patent document	Capacitors Some embodiments include methods of forming capacitors. A metal oxide mixture may be formed over a first capacitor electrode. The metal oxide mixture may have a continuous concentration gradient of a second...	31-Jan-2012
14	US 8105862 B2 patent document	Imager with tuned color filter An optimized color filter array is formed in, above or below one or more damascene layers. The color filter array includes filter regions which are configured to optimize the combined optical properties of the...	31-Jan-2012
15	US 8107305 B2 patent document	Integrated circuit memory operation apparatus and methods Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer...	31-Jan-2012
16	US 8105896 B2 patent document	Methods of forming capacitors A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive...	31-Jan-2012
17	US 8106644 B2 patent document	Reference circuit with start-up control, generator, device, system and method including same A reference generator circuit generates a reference signal for use by a regulator in generating operational power for circuits and devices. A start-up circuit includes a self-biased voltage reference and a...	31-Jan-2012
18	US 8107296 B2 patent document	Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed...	31-Jan-2012
19	US 8105131 B2 patent document	Method and apparatus for removing material from microfeature workpieces Methods and apparatus for removing materials from microfeature workpieces. One embodiment of a subpad in accordance with the invention comprises a matrix having a first surface configured to support a polishing...	31-Jan-2012
20	US 8105858 B2 patent document	CMOS imager having a nitride dielectric An imaging device formed as a CMOS semiconductor integrated circuit includes a nitrogen containing insulating material beneath a photogate. The nitrogen containing insulating material, preferably be one of a...	31-Jan-2012
21	US 8106488 B2 patent document	Wafer level packaging Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the...	31-Jan-2012
22	US 8105956 B2 patent document	Methods of forming silicon oxides and methods of forming interlevel dielectrics A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising...	31-Jan-2012
23	US 2012/0019293 A1 patent application	Delay lock loop phase glitch error filter A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a...	26-Jan-2012
24	US 2012/0023294 A1 patent application	Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing...	26-Jan-2012
25	US 2012/0021587 A1 patent application	Systems and Methods for Forming Metal Oxide Layers A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process...	26-Jan-2012
26	US 2012/0021573 A1 patent application	Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced...	26-Jan-2012
27	US 2012/0018693 A1 patent application	Confined resistance variable memory cell structures and methods Confined resistance variable memory cell structures and methods are described herein. One or more methods of forming a confined resistance variable memory cell structure includes forming a via in a memory cell...	26-Jan-2012
28	US 2012/0018789 A1 patent application	Systems and Devices Including Multi-Gate Transistors and Methods of Using, Making, and Operating the Same Disclosed are methods of forming transistors. In one embodiment, the transistors are formed by forming a plurality of elliptical bases in a substrate and forming fins form the elliptical bases. The transistors...	26-Jan-2012
29	US 2012/0018887 A1 patent application	Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side,...	26-Jan-2012
30	US 2012/0019349 A1 patent application	Confined resistance variable memory cells and methods Methods, devices, and systems associated with resistance variable memory device structures are described herein. In one or more embodiments, a method of forming a confined resistance variable memory cell...	26-Jan-2012
31	US 2012/0021601 A1 patent application	Methods of Forming Through Substrate Interconnects A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line...	26-Jan-2012
32	US 2012/0021594 A1 patent application	Methods of Forming a Plurality of Transistor Gates, and Methods of Forming a Plurality of Transistor Gates Having at Least Two Different Work Functions A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width...	26-Jan-2012
33	US 2012/0021610 A1 patent application	Methods of Forming Material on a Substrate, and a Method of Forming a Field Effect Transistor Gate Oxide on a Substrate The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first species monolayer is chemisorbed onto a substrate...	26-Jan-2012
34	US 8101261 B2 patent document	One-dimensional arrays of block copolymer cylinders and applications thereof Methods for fabricating sublithographic, nanoscale microstructures in one-dimensional arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.	24-Jan-2012
35	US 8102006 B2 patent document	Different gate oxides thicknesses for different transistors in an integrated circuit An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide...	24-Jan-2012
36	US 8102295 B2 patent document	Integrators for delta-sigma modulators Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line...	24-Jan-2012
37	US 8102707 B2 patent document	Non-volatile multilevel memory cells The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line,...	24-Jan-2012
38	US 8102710 B2 patent document	System and method for setting access and modification for synchronous serial interface NAND The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One...	24-Jan-2012
39	US 8103898 B2 patent document	Explicit skew interface for mitigating crosstalk and simultaneous switching noise Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree...	24-Jan-2012
40	US 8103928 B2 patent document	Multiple device apparatus, systems, and methods Data digits and correction digits are received in each of a number of integrated circuit (IC) devices. Apparatus, systems, and methods are disclosed that operate to check the data digits for error in each IC...	24-Jan-2012
41	US 8101936 B2 patent document	SnSe-based limited reprogrammable cell Methods and apparatus for providing a memory device that can be programmed a limited number of times. According to exemplary embodiments, a memory device and its method of formation provide a first electrode, a...	24-Jan-2012
42	US 8102706 B2 patent document	Programming a memory with varying bits per cell Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals...	24-Jan-2012
43	US 8102906 B2 patent document	Fractional-rate decision feedback equalization useful in a data transmission system Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a one-half-rate clocked DFE circuit utilizes two input data...	24-Jan-2012
44	US 8101454 B2 patent document	Method of forming pixel cell having a grated interface A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with said silicon substrate, and a method of fabricating...	24-Jan-2012
45	US 8102723 B2 patent document	Memory device bit line sensing system and method that compensates for bit line resistance variations Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for...	24-Jan-2012
46	US 8101459 B2 patent document	Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween A method for assembling semiconductor devices includes providing a first semiconductor device, securing spacers to noncircuit bond pads of the first semiconductor device, and positioning a second semiconductor...	24-Jan-2012
47	US 8101497 B2 patent document	Self-aligned trench formation Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set trenches. Methods taught herein can be used as a pitch doubling...	24-Jan-2012
48	US 8101992 B2 patent document	Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned...	24-Jan-2012
49	US 8102013 B2 patent document	Lanthanide doped TiOx films The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOX) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium,...	24-Jan-2012
50	US 8101464 B2 patent document	Microelectronic devices and methods for manufacturing microelectronic devices Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an...	24-Jan-2012
51	US 8102715 B2 patent document	Power-off apparatus, systems, and methods Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For...	24-Jan-2012
52	US 8103936 B2 patent document	System and method for data read of a synchronous serial interface NAND A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the...	24-Jan-2012
53	US 8102008 B2 patent document	Integrated circuit with buried digit line A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the...	24-Jan-2012
54	US 8102709 B2 patent document	Transistor having peripheral channel Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain region formed...	24-Jan-2012
55	US 8103805 B2 patent document	Configuration finalization on first valid NAND command A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the receipt of a valid command to the memory device....	24-Jan-2012
56	US 8103940 B2 patent document	Programming error correction code into a solid state memory device with varying bits per cell Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to...	24-Jan-2012
57	US 8101903 B2 patent document	Method, apparatus and system providing holographic layer as micro-lens and color filter array in an imager A method, apparatus, and system that provides a holographic layer as a micro-lens array and/or a color filter array in an imager. The method of writing the holographic layer results in overlapping areas in the...	24-Jan-2012
58	US 8102700 B2 patent document	Unidirectional spin torque transfer magnetic memory cell structure Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a...	24-Jan-2012
59	US 2012/0013273 A1 patent application	Solid state lighting devices without converter materials and associated methods of manufacturing Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second...	19-Jan-2012
60	US 2012/0013314 A1 patent application	Voltage regulator system The present disclosure includes circuits, systems and methods for regulating voltage. One voltage regulator system embodiment includes a voltage regulator having an output and a number of stages coupled in...	19-Jan-2012
61	US 2012/0016650 A1 patent application	Simulating the Transmission and Simultaneous Switching Output Noise of Signals in a Computer System Methods implementable in a computer system for simulating the transmission of signals across a plurality of data channels (bus) are disclosed. The disclosed techniques simulate the effects of Intersymbol...	19-Jan-2012
62	US 2012/0015526 A1 patent application	Silicon Dioxide Deposition Methods Using at Least Ozone and TEOS as Deposition Precursors Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition...	19-Jan-2012
63	US 2012/0016651 A1 patent application	Simulating the Transmission of Asymmetric Signals in a Computer System Methods implementable in a computer system for simulating the transmission of signals are disclosed. The disclosed techniques simulate the effect of the transmitter as well as the channel on a positive and...	19-Jan-2012
64	US 2012/0012855 A1 patent application	Solid-state light emitters having substrates with thermal and electrical conductivity enhancements and method of manufacture Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved thermal conductivity between a solid-state light...	19-Jan-2012
65	US 2012/0012921 A1 patent application	Memory arrays having substantially vertical, adjacent semiconductor structures and the formation thereof Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the...	19-Jan-2012
66	US 2012/0012812 A1 patent application	Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a...	19-Jan-2012
67	US 2012/0014166 A1 patent application	Resistive memory The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least...	19-Jan-2012
68	US 2012/0012914 A1 patent application	Semiconductor Constructions, and Methods of Forming Semiconductor Constructions The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and...	19-Jan-2012
69	US 2012/0013368 A1 patent application	Method and system for electrically coupling a chip to chip package A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the...	19-Jan-2012
70	US 2012/0014185 A1 patent application	Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias...	19-Jan-2012
71	US 2012/0015524 A1 patent application	Process for Enhancing Solubility and Reaction Rates In Supercritical Fluids Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films...	19-Jan-2012
72	US 8097537 B2 patent document	Phase change memory cell structures and methods Phase change memory cell structures and methods are described herein. A number of methods of forming a phase change memory cell structure include forming a dielectric stack structure on a first electrode,...	17-Jan-2012
73	US 8097908 B2 patent document	Antiblooming imaging apparatus, systems, and methods Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge...	17-Jan-2012
74	US 8098530 B2 patent document	Systems and methods for erasing a memory Methods of erasing a memory, methods of operating a memory, memory devices, and systems. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final erase...	17-Jan-2012
75	US 8099366 B2 patent document	Software distribution method and apparatus The present invention provides for a method and apparatus for distributing digital information, such as software applications, to application users. By providing the digital information on unused memory space...	17-Jan-2012
76	US 8097910 B2 patent document	Vertical transistors The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops...	17-Jan-2012
77	US 8099543 B2 patent document	Methods of operarting memory devices within a communication protocol standard timeout requirement The present disclosure includes methods and devices for logical memory blocks. One method for operating a memory device includes receiving a command to operate X pages of the memory device, X being greater than...	17-Jan-2012
78	US 8097506 B2 patent document	Shallow trench isolation for a memory In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may...	17-Jan-2012
79	US 8097947 B2 patent document	Conductive systems and devices including wires coupled to anisotropic conductive film, and methods of forming the same Methods and apparatus for eliminating wire sweep and shorting while avoiding the use of under-bump metallization and high cost attendant to the use of conventional redistribution layers. An anisotropically...	17-Jan-2012
80	US 8097175 B2 patent document	Method for selectively permeating a self-assembled block copolymer, method for forming metal oxide structures, method for forming a metal oxide pattern, and method for patterning a semiconductor structure Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. The metal oxide structures and patterns may be...	17-Jan-2012
81	US 8098529 B2 patent document	Memory device having buried boosting plate and methods of operating the same Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI...	17-Jan-2012
82	US 8098180 B2 patent document	Devices including analog-to-digital converters for internal data storage locations A device that includes an internal data storage location coupled to an electrical conductor and an analog-to-digital converter coupled to the internal data storage location via the electrical conductor. In some...	17-Jan-2012
83	US 2012/0007209 A1 patent application	Semiconductor device structures including damascene trenches with conductive structures and related method A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with...	12-Jan-2012
84	US 2012/0007256 A1 patent application	Redistribution layers for microfeature workpieces, and associated systems and methods Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution...	12-Jan-2012
85	US 2012/0008399 A1 patent application	Methods of operating memories including characterizing memory cell signal lines Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available....	12-Jan-2012
86	US 2012/0008409 A1 patent application	Reduction of quick charge loss effect in a memory device Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to...	12-Jan-2012
87	US 2012/0011409 A1 patent application	Devices, methods, and apparatuses for detection, sensing, and reporting functionality for semiconductor memory Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least...	12-Jan-2012
88	US 2012/0008404 A1 patent application	System and method for reducing pin-count of memory devices, and memory device testers for same Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data...	12-Jan-2012
89	US 2012/0008440 A1 patent application	Data retention kill function Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or...	12-Jan-2012
90	US 2012/0009779 A1 patent application	Contact formation The present disclosure includes various methods of contact embodiments. One such method embodiment includes forming a trench in an insulator stack material of a particular thickness. This method includes...	12-Jan-2012
91	US 2012/0009793 A1 patent application	Method for selectively modifying spacing between pitch multiplied structures Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and...	12-Jan-2012
92	US 2012/0007037 A1 patent application	Cross-point memory utilizing ru/Si diode Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further...	12-Jan-2012
93	US 2012/0009776 A1 patent application	Semiconductor substrates with unitary vias and via terminals, and associated systems and methods Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in...	12-Jan-2012
94	US 2012/0011335 A1 patent application	Memory controllers, memory systems, solid state drives and methods for processing a number of commands The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively...	12-Jan-2012
95	US 8093643 B2 patent document	Multi-resistive integrated circuit memory A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the...	10-Jan-2012
96	US 8093937 B2 patent document	Seamless coarse and fine delay structure for high performance DLL A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and fine delays. The system may use a single coarse...	10-Jan-2012
97	US 8093666 B2 patent document	Lanthanide yttrium aluminum oxide dielectric films Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium...	10-Jan-2012
98	US 8093730 B2 patent document	Underfilled semiconductor die assemblies and methods of forming the same An apparatus and method may be used for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide a robust, inflexible cost-effective bond. The...	10-Jan-2012
99	US 8095765 B2 patent document	Memory block management Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two...	10-Jan-2012
100	US 8093638 B2 patent document	Systems with a gate dielectric having multiple lanthanide oxide layers Electronic systems and methods of forming the electronic systems include a gate dielectric having multiple lanthanide oxide layers. Such electronic systems may be used in a variety of electronic system...	10-Jan-2012

Showing 1-100 of 26954 results

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