Texas Instruments

Showing 201-300 of 24645 results

<<	<	Page:	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	>	>>

No	Document	Title	Date
201	US 2011/0291263 A1 patent application	Ic having dielectric polymeric coated protruding features having wet etched exposed tips A method of fabricating IC die includes providing a substrate having a topside semiconductor surface including active circuitry and a bottomside surface. The IC die includes at least one protruding feature...	01-Dec-2011
202	US 2011/0292692 A1 patent application	Opto-coupled sensing The present invention provides an isolated regulating power converter with opto-coupled feedback of output (Vo) with respect to a reference level (Vset) for regulation to a converter controller. The sense of...	01-Dec-2011
203	US 8067279 B2 patent document	Application of different isolation schemes for logic and embedded memory The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation...	29-Nov-2011
204	US 8068379 B1 patent document	Dynamic RAM A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected...	29-Nov-2011
205	US 8067795 B2 patent document	Single poly EEPROM without separate control gate nor erase regions A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain regions, which defines a source-to-floating gate...	29-Nov-2011
206	US 8068043 B2 patent document	Method and apparatus for video processing in context-adaptive binary arithmetic coding A method and apparatus of a digital signal processor for coding of a significant map. The method for coding of a significant map includes carrying out a scan of at least a portion of a block of transform...	29-Nov-2011
207	US 8068267 B2 patent document	Speckle reduction in display systems that employ coherent light sources Speckle effect in display system is reduced by utilizing the instability of phase-coherent light and the transmission of the instable phase-coherent light through a multi-mode optical fiber with a suitable...	29-Nov-2011
208	US 8067792 B2 patent document	Memory device with memory cell including MuGFET and FIN capacitor One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also...	29-Nov-2011
209	US 8067955 B2 patent document	Preventing erroneous operation in a system where synchronized operation is required This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention senses the...	29-Nov-2011
210	US 8068871 B2 patent document	Systems and methods for time optimization for silencing wireless devices in coexistence networks Embodiments provide systems and methods to optimize the time when to transmit a silencing frame, and hence, improve the overall network throughput and avoid access point transmission rate fall-back mechanism...	29-Nov-2011
211	US 8069201 B2 patent document	8×8 transform and quantization Low complexity (16 bit arithmetic) video compression has 8×8 block with transforms using 8×8 integer matrices and quantization with look up table scalar plus constant right shift for all quantization steps....	29-Nov-2011
212	US 8069290 B2 patent document	Processing system operable in various execution environments A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security...	29-Nov-2011
213	US 8068466 B2 patent document	Transmission of multiple information elements in multiple channels A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations. The transmission from the secondary to primary node in a wireless network is performed by...	29-Nov-2011
214	US 2011/0285439 A1 patent application	Digital to Frequency Synthesis Using Flying-Adder with Dithered Command Input To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock...	24-Nov-2011
215	US 2011/0289371 A1 patent application	Low power scan and delay test method and apparatus Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low...	24-Nov-2011
216	US 2011/0289370 A1 patent application	Optimized jtag interface An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional...	24-Nov-2011
217	US 2011/0285451 A1 patent application	Precision voltage divider A circuit for producing a quotient of two input voltages, Vy and Vx has a resistor across which said two input voltages are selectively successively applied. An operational amplifier has a reference potential...	24-Nov-2011
218	US 2011/0285745 A1 patent application	Method and apparatus for touch screen assisted white balance A method and apparatus for performing automatic white balance utilizing a touch screen. The method includes determining an area on a touch screen for performing automatic white balance, extracting portion of a...	24-Nov-2011
219	US 2011/0285423 A1 patent application	Simultaneous lvds i/O signaling method and apparatus First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver...	24-Nov-2011
220	US 2011/0286247 A1 patent application	Sensing arrangements A sensing arrangement and method a sense winding is used to provide a voltage which represents the voltage appearing across an in-circuit magnetic component. In a flyback phase, when the component is supplying...	24-Nov-2011
221	US 2011/0285449 A1 patent application	Apparatus and method for efficient level shift An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first...	24-Nov-2011
222	US 8065505 B2 patent document	Stall-free pipelined cache for statically scheduled and dispatched execution This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency...	22-Nov-2011
223	US 8063911 B2 patent document	System and method for gamut mapping of out-of-gamut signals A system and method for gamut mapping out-of-gamut signals. A method includes adjusting each color in a color signal, determining a maximum color value of the color signal, in response to a determining that the...	22-Nov-2011
224	US 8065506 B2 patent document	Application specific instruction set processor for digital radio processor receiving chain signal processing This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application....	22-Nov-2011
225	US 8063949 B2 patent document	Activity-based system and method for reducing gain imbalance in a bayer pattern and digital camera employing the same An activity-based system for, and method of, reducing Gr-Gb gain imbalance and a digital camera incorporating the system or the method. In one embodiment, the system includes: (1) a sensor configured to provide...	22-Nov-2011
226	US 8064546 B2 patent document	Random access preamble detection for long term evolution wireless networks This invention is a method for preamble detection with estimation of UE timing advance (TA) and channel quality information (CQI) which uses a sliding window to detect the preamble and estimate user timing...	22-Nov-2011
227	US 8063948 B2 patent document	Proximity-based system and method for reducing gain imbalance in a bayer pattern and digital camera employing the same A proximity-based system for, and method of, reducing Gr-Gb gain imbalance and a digital camera incorporating the system or the method. In one embodiment, the system includes: (1) a sensor configured to provide...	22-Nov-2011
228	US 8064279 B2 patent document	Structure and method for screening SRAMS An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages...	22-Nov-2011
229	US 8064611 B2 patent document	Uplink noise cancellation A system comprising audio logic adapted to convert captured sound into an audio signal. The system also comprises transmission logic which causes noise to be added to the audio signal. The system further...	22-Nov-2011
230	US 8065140 B2 patent document	Method and system for determining predominant fundamental frequency Methods, digital systems, and computer readable media are provided for determining a predominant fundamental frequency of a frame of an audio signal by finding a maximum absolute signal value in history data...	22-Nov-2011
231	US 8065577 B2 patent document	Dual controllers for scan paths, distributors, and collectors Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and...	22-Nov-2011
232	US 8064717 B2 patent document	Digital camera and method Deblurring of digital camera images by estimating the blur function from an image extracted from a video sequence taken about the time of an image capture. The extracted image is selected to be the sharpest of...	22-Nov-2011
233	US 8065578 B2 patent document	Inverted TCK access port selector selecting one of plural TAPs The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved...	22-Nov-2011
234	US 8064271 B2 patent document	Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in rows and columns, (2) bit lines associated with...	22-Nov-2011
235	US 8062966 B2 patent document	Method for integration of replacement gate in CMOS flow Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability...	22-Nov-2011
236	US 8063688 B2 patent document	AC clamp circuit for video applications This invention is a clamp circuit for a video input. The clamp circuit includes: a coupling capacitor; a differential amplifier comparing a video input to predetermined reference voltage; a clamp transistor...	22-Nov-2011
237	US 8064275 B2 patent document	Local sensing and feedback for an SRAM array An integrated circuit having an SRAM array includes SRAM cells arranged in rows and columns, and a global read circuit connected to globally read SRAM cells corresponding to accessed rows and columns of the...	22-Nov-2011
238	US 2011/0280261 A1 patent application	Interleaver Design and Header Structure For ITU G.hnem Embodiments of the invention provide an interleaver design and header fields for ITU-T G.hnem. The header may comprise two parts that are separately encoded. A common header segment is encoded alone, and an...	17-Nov-2011
239	US 2011/0283154 A1 patent application	Adapting scan-bist architectures for low power operation A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST...	17-Nov-2011
240	US 2011/0279297 A1 patent application	Analog-to-Digital Conversion One embodiment of the present invention includes an analog-to-digital converter (ADC) system. The system includes an ADC configured to generate digital samples that are digital versions of at least one analog...	17-Nov-2011
241	US 2011/0280314 A1 patent application	Slice encoding and decoding processors, circuits, devices, systems and processes A video decoder includes a memory (140) operable to hold entropy coded video data accessible as a bit stream, a processor (100) operable to issue at least one command for loose-coupled support and to issue at...	17-Nov-2011
242	US 2011/0278693 A1 patent application	High-voltage variable breakdown voltage (Bv) diode for electrostatic discharge (Esd) applications Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree...	17-Nov-2011
243	US 2011/0278936 A1 patent application	Low dropout regulator with multiplexed power supplies Generally, with low drop out (LDO) regulators that use multiplexed power supplies, the transistors within the regulator can use a substantial amount of area. Here, a regulator is provided that uses a...	17-Nov-2011
244	US 2011/0279170 A1 patent application	Embedded sar based active gain capacitance measurement system and method A system for measuring a capacitor (CSENj) precharges a CDAC (23) in a SAR converter (17) to a reference voltage (VAZ) and also precharges a first terminal (3-j) of the capacitor to another reference voltage...	17-Nov-2011
245	US 2011/0279651 A1 patent application	Method and Apparatus for Auto-Convergence Based on Auto-Focus Point for Stereoscopic Frame A method and apparatus for performing auto-convergence on a frame of a stereoscopic image or video based on at least one auto-focus point. The method includes retrieving a location of focus points from the...	17-Nov-2011
246	US 2011/0282639 A1 patent application	Modeling of Non-Quasi-Static Effects During Hot Carrier Injection Programming of Non-Volatile Memory Cells A non-quasi-static model of the programming behavior of a floating-gate metal-oxide-semiconductor (MOS) transistor. This model is based on evaluation of a body current, for example determined as a function of...	17-Nov-2011
247	US 2011/0281433 A1 patent application	Etching method using an at least semi-solid media An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch...	17-Nov-2011
248	US 2011/0280312 A1 patent application	Video processing device with memory optimization in image post-processing A video processing device is disclosed that includes a processor unit with a processor and a memory having a reorder buffer. The processor includes a reorder module, a frame rate conversion module, and...	17-Nov-2011
249	US 2011/0281593 A1 patent application	High resolution, low power design for cpri/Obsai latency measurement As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links....	17-Nov-2011
250	US 8058677 B2 patent document	Stress buffer layer for ferroelectric random access memory An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a...	15-Nov-2011
251	US 8059340 B2 patent document	Method and system for reducing speckle by vibrating a line generating element Provided is a method and system for reducing speckle in an image produced from a light source. The method, in one embodiment, includes providing a line generating element, the line generating element having a...	15-Nov-2011
252	US 8059524 B2 patent document	Allocation and logical to physical mapping of scheduling request indicator channel in wireless networks A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is transmitted from a NodeB in a cell to UE within the...	15-Nov-2011
253	US 8059670 B2 patent document	Hardware queue management with distributed linking information A network element including a processor with logic for managing packet queues by way of packet descriptor index values that are mapped to addresses in the memory space of the packet descriptors. A linking...	15-Nov-2011
254	US 8059917 B2 patent document	3-D modeling A system comprising an imaging device adapted to capture images of a target object at multiple angles. The system also comprises storage coupled to the imaging device and adapted to store a generic model of the...	15-Nov-2011
255	US 8060027 B2 patent document	RF transmission leakage mitigator, method of mitigating an RF transmission leakage and CDMA transceiver employing the same The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator...	15-Nov-2011
256	US 8058706 B2 patent document	Delamination resistant packaged die having support and shaped die having protruding lip on support A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ≧5%...	15-Nov-2011
257	US 8059745 B2 patent document	Sharing logic circuitry for a maximum likelihood MIMO decoder and a viterbi decoder A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are modulated according to Orthogonal Frequency Division...	15-Nov-2011
258	US 8058161 B2 patent document	Recessed STI for wide transistors A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench...	15-Nov-2011
259	US 8059764 B2 patent document	Systems and methods for low-complexity max-log MIMO detection Embodiments provide novel systems and methods for multiple-input multiple-output (MIMO) Max-Log detection. These systems and methods enable near-optimal performance with low complexity for a two-input...	15-Nov-2011
260	US 8058122 B2 patent document	Formation of metal gate electrode using rare earth alloy incorporated into mid gap metal Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a...	15-Nov-2011
261	US 8058860 B2 patent document	Single pin multi-VID bit interface circuit for dynamic voltage change of a DC/DC converter A controller for a DC/DC converter is provided. The controller comprises an error circuit, control logic, a high side driver, a low side driver, and an interface circuit. The error circuit is coupled to a...	15-Nov-2011
262	US 8058902 B1 patent document	Circuit for aligning input signals A circuit for aligning input signals includes a clock generating circuit (CGC) responsive to first signal and second signal to generate a clock signal. A first flip flop and a second flip flop, coupled to the...	15-Nov-2011
263	US 8059323 B2 patent document	Stabilizer for MEMS devices having deformable elements A stabilizer mechanism is coupled to a deformable element of a microelectromechanical device for reducing unwanted deformation of the deformable element by increasing the stiffness of the deformable element in...	15-Nov-2011
264	US 8060929 B2 patent document	Method and system for providing security to processors There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not...	15-Nov-2011
265	US RE42919 E1 patent document	Power control with space time transmit diversity A circuit is designed with a measurement circuit (432). The measurement circuit is coupled to receive a first input signal (903) from a first antenna (128) of a transmitter and coupled to receive a second input...	15-Nov-2011
266	US 8060019 B2 patent document	Asymmetric ESD protection for FM transmitter Various apparatuses and methods for protecting a transmitter from electrostatic discharge are disclosed herein. For example, some embodiments provide an apparatus including a first ESD clamp connected to an...	15-Nov-2011
267	US 8059735 B2 patent document	Allocation of block spreading sequences A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations. The transmission from the secondary to primary node in a wireless network is obtained using a...	15-Nov-2011
268	US 8059746 B2 patent document	Producing STTD diversity signal from rake combined level 3 message A circuit is designed with a measurement circuit (746) coupled to receive an input signal from at least one of a first antenna and a second antenna of a transmitter. The measurement circuit produces an output...	15-Nov-2011
269	US 2011/0275168 A1 patent application	Single step cmp for polishing three or more layer film stacks A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide...	10-Nov-2011
270	US 2011/0272449 A1 patent application	Dual Capillary IC Wirebonding The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual capillary bond head. The separate wires are preferably...	10-Nov-2011
271	US 2011/0273186 A1 patent application	Circuit for controlling temperature and enabling testing of a semiconductor chip A circuit for controlling temperature of a semiconductor chip includes a first heating element that is built into the semiconductor chip. The first heating element generates heat to increase the temperature of...	10-Nov-2011
272	US 2011/0273946 A1 patent application	Universal test structures based sram on-chip parametric test module and methods of operating and testing An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first...	10-Nov-2011
273	US 2011/0273204 A1 patent application	Parallel scan distributors and collectors and process of testing integrated circuits An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to...	10-Nov-2011
274	US 2011/0276216 A1 patent application	Automotive cruise controls, circuits, systems and processes A cruise control includes an input (225) for speed-related data, a hill angle sensor (230), and a cruise controller (210) having a throttling control output (215) and control conditions responsive to both the...	10-Nov-2011
275	US 2011/0275210 A1 patent application	Method of making vertical transistor with graded field plate dielectric An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode...	10-Nov-2011
276	US 2011/0273217 A1 patent application	Voltage generating circuit for an attenuator A circuit includes a digital-to-analog converter (DAC), coupled to a power supply, that provides a first current at a first output terminal of the DAC and a second current at a second output terminal of the...	10-Nov-2011
277	US 2011/0276847 A1 patent application	Shadow access port method and apparatus The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and...	10-Nov-2011
278	US 2011/0276731 A1 patent application	Dual-port functionality for a single-port cell memory device A network node (5) including a line card (20) for packet-based data communications is disclosed. The line card (20) includes a transmit FIFO buffer (24T) and a receive FIFO buffer (24R), for buffering...	10-Nov-2011
279	US 8054057 B2 patent document	Low dropout regulator testing system and device A device for testing low dropout (LDO) regulator is disclosed. In one embodiment, a device for testing LDO regulators includes an absolute value measurement module for measuring absolute output voltages of the...	08-Nov-2011
280	US 8054552 B2 patent document	Lens array element and method According to one embodiment of the present invention a method for directing light onto a digital micromirror device is disclosed that includes the steps of directing light toward a DMD through a lens that...	08-Nov-2011
281	US 8054912 B2 patent document	Large-dynamic-range lookup table for a transmitter predistorter and system and method employing the same A predistorters for use with a nonlinear element and methods of predistorting for a nonlinear element for use in a 3G, e.g., WCDMA transmitter. In one embodiment, the predistorter includes: (1) a lookup table...	08-Nov-2011
282	US 8052286 B2 patent document	System and method for utilizing a scanning beam to display an image A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first dimension of a first length and a second dimension...	08-Nov-2011
283	US 8054823 B2 patent document	Mapping schemes for secondary synchronization signal scrambling Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to...	08-Nov-2011
284	US 8055947 B2 patent document	Comparing supplied and sampled link ID bits on TMS lead An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system,...	08-Nov-2011
285	US 8055967 B2 patent document	TAP interface outputs connected to TAP interface inputs An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be...	08-Nov-2011
286	US 8054103 B1 patent document	Synchronous clock multiplexing and output-enable A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided...	08-Nov-2011
287	US 8054529 B2 patent document	System and method for displaying images System and method for simultaneous display of multiple images using a single light modulator array. A preferred embodiment comprises a light source that produces a light with desired spectral characteristics, a...	08-Nov-2011
288	US 8055962 B2 patent document	Testing IC functional and test circuitry having separate input/output pads Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is...	08-Nov-2011
289	US 8053252 B2 patent document	Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A...	08-Nov-2011
290	US 8053256 B2 patent document	Variable thickness single mask etch process The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a...	08-Nov-2011
291	US 8053322 B2 patent document	Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the...	08-Nov-2011
292	US 8053873 B2 patent document	IC having voltage regulated integrated Faraday shield An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the...	08-Nov-2011
293	US 8054810 B2 patent document	Interleaver for transmit diversity The present invention exploits the benefits obtainable from using transmit diversity by designing the size of the interleaver matrix to avoid the case where most or all of the bits in a row are transmitted on a...	08-Nov-2011
294	US 8055231 B2 patent document	RF feedback engine coupled to receiver low noise amplifier Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to amplify received analog RF signals and a...	08-Nov-2011
295	US 8055828 B2 patent document	Electronic power management system An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having...	08-Nov-2011
296	US 8054358 B2 patent document	Solid state image pickup device This invention improves linearity of a solid-state image pickup device beyond that of the prior art source follower to improve image quality. The image pickup device has plural pixels disposed in an array. Each...	08-Nov-2011
297	US 8053324 B2 patent document	Method of manufacturing a semiconductor device having improved transistor performance In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by conducting a pre-deposition spacer deposition...	08-Nov-2011
298	US 8054742 B2 patent document	System and method for sidelobe suppression in communications systems A system and method for sidelobe suppression in OFDM communications systems is provided. A method for transmitting an information symbol having a plurality of information sub-carriers and a plurality of active...	08-Nov-2011
299	US 8055217 B2 patent document	Adaptive complex gain predistorter for a transmitter Symbols are transmitted in a Cartesian transmitter by pre-distorting an input signal X having in-phase and quadrature components using a first compensation lookup table operable to hold complex valued entries...	08-Nov-2011
300	US 8055886 B2 patent document	Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first...	08-Nov-2011

Showing 201-300 of 24645 results

<<	<	Page:	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	>	>>