| No | Document | Title | Date |
|---|---|---|---|
| 301 |
US 8056029 B2
patent document
|
Merging sub-resolution assist features of a photolithographic mask
Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second sub-resolution...
|
08-Nov-2011 |
| 302 |
US 8054914 B2
patent document
|
Noise variance estimation
A method and system for estimating noise variance. A method for noise variance estimation comprises receiving a first multi-sample symbol and receiving a second multi-sample symbol. The first multi-sample...
|
08-Nov-2011 |
| 303 |
US 8053296 B2
patent document
|
Capacitor formed on a recrystallized polysilicon layer
The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a...
|
08-Nov-2011 |
| 304 |
US 8053285 B2
patent document
|
Thermally enhanced single inline package (SIP)
In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A leadframe (210, 310, 410) having a die pad (220, 320,...
|
08-Nov-2011 |
| 305 |
US 8053876 B2
patent document
|
Multi lead frame power package
According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead frame, and a second lead frame. The die is disposed...
|
08-Nov-2011 |
| 306 |
US 8054056 B2
patent document
|
Frequency regulated hysteretic average current mode converter
A switch mode power converter that precisely controls average switching current and operating frequency. The switching control operative in hysteretic average current mode control provides wide bandwidth...
|
08-Nov-2011 |
| 307 |
US 8054652 B2
patent document
|
Systems and methods for off-time control in a voltage converter
Various embodiments of the present invention provide voltage converters and methods for using such. As one example, a voltage converter is disclosed that includes a transformer with a first winding and a second...
|
08-Nov-2011 |
| 308 |
US 8054861 B2
patent document
|
Primary, secondary, and tertiary codes synchronizing slots in a frame
A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method...
|
08-Nov-2011 |
| 309 |
US 8053349 B2
patent document
|
BGA package with traces for plating pads under the chip
A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net...
|
08-Nov-2011 |
| 310 |
US 2011/0267146 A1
patent application
|
Open loop coarse tuning for a pll
In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of...
|
03-Nov-2011 |
| 311 |
US 2011/0267177 A1
patent application
|
Effective Low Voltage to Medium Voltage Transmission on PRIME Band
Coupling and interface circuits for powerline modems are disclosed. A powerline modem may be coupled to a low voltage (LV) line or a medium voltage (MV) line using a circuit that is designed to compensate for...
|
03-Nov-2011 |
| 312 |
US 2011/0266693 A1
patent application
|
Tce compensation for package substrates for reduced die warpage assembly
A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package...
|
03-Nov-2011 |
| 313 |
US 2011/0268289 A1
patent application
|
Ground loop noise rejection for a headset subsystem
For headphone subsystems that employ common ground switches for speaker outputs (for example), there can be a significant issue with cross-talk and ground noise. Here, configurations for an amplifier and switch...
|
03-Nov-2011 |
| 314 |
US 2011/0271160 A1
patent application
|
Accelerating scan test by re-using response data as stimulus data abstract
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus...
|
03-Nov-2011 |
| 315 |
US 2011/0266624 A1
patent application
|
Electrostatic discharge protection having multiply segmented diodes in proximity to transistor
An ESD protection device for an I/O pad (401); the device comprising a MOS transistor (420) having at least one elongated source region (422) and at least one elongated drain region (421) in a substrate (400)...
|
03-Nov-2011 |
| 316 |
US 8051285 B2
patent document
|
Battery processor circuitry with separate public and private bus
Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In one embodiment, the system for providing a battery...
|
01-Nov-2011 |
| 317 |
US 8051351 B2
patent document
|
DDR circuit with addressable TAP linking circuitry and plural TAPS
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the...
|
01-Nov-2011 |
| 318 |
US 8049562 B2
patent document
|
Amplifier with improved input resistance and controlled common mode
An amplifier includes a first pair of transistors (the first pair) that defines a first output, each transistor of the first pair having a gate coupled to a first input terminal; a second pair of transistors...
|
01-Nov-2011 |
| 319 |
US 8050368 B2
patent document
|
Nonlinear adaptive phase domain equalization for multilevel phase coded demodulators
A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the immunity of phase-modulated signals (PSK) to...
|
01-Nov-2011 |
| 320 |
US 8051347 B2
patent document
|
Scan-enabled method and system for testing a system-on-chip
Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of the SoC. The SoC includes multiple cores. Each...
|
01-Nov-2011 |
| 321 |
US 8051349 B2
patent document
|
Link instruction register with instruction register, and gate and multiplexer
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test...
|
01-Nov-2011 |
| 322 |
US 8048358 B2
patent document
|
Pop semiconductor device manufacturing method
The objective of the invention is to prevent electrostatic destruction of semiconductor chips during resin molding. With the semiconductor device manufacturing method, a substrate 400 that includes on the...
|
01-Nov-2011 |
| 323 |
US 8049320 B2
patent document
|
Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom
A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top...
|
01-Nov-2011 |
| 324 |
US 8049534 B2
patent document
|
Low-power high-speed differential driver with precision current steering
In bipolar CMOS or BiCMOS process technologies, drivers (such as mixed mode or hybrid mode drivers) using both bipolar and CMOS transistors (i.e., field effect transistors or FETs) may have undesirable...
|
01-Nov-2011 |
| 325 |
US 8049214 B2
patent document
|
Degradation correction for finFET circuits
A pair of split-gate fin field effect transistors (finFETs) in an IC, each containing a signal gate and a control gate, in which an adjustable voltage source, preferably in the form of a...
|
01-Nov-2011 |
| 326 |
US 8049555 B2
patent document
|
Low leakage sampling switch
An electronic device includes a cascade of a plurality of transistors. Each transistor of the cascade receives an input voltage at a first terminal of its source/drain channel and receives a sampling clock...
|
01-Nov-2011 |
| 327 |
US 8049946 B2
patent document
|
Lubricating micro-machined devices using fluorosurfactants
A method of lubricating MEMS devices using fluorosurfactants 42. Micro-machined devices, such as a digital micro-mirror device (DMD™) 940, which make repeated contact between moving parts, require lubrication...
|
01-Nov-2011 |
| 328 |
US 8050375 B2
patent document
|
Digital phase locked loop with integer channel mitigation
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a...
|
01-Nov-2011 |
| 329 |
US 8050934 B2
patent document
|
Local pitch control based on seamless time scale modification and synchronized sampling rate conversion
This invention locally controls the pitch of speech and audio signals. The invention is based on a seamless time scale modification (S-TSM) scheme connected to a synchronized sampling rate converter that...
|
01-Nov-2011 |
| 330 |
US 8051391 B2
patent document
|
Method for layout of random via arrays in the presence of strong pitch restrictions
Exemplary embodiments provide a method for laying out an integrated circuit (“IC”) design and the IC design layout. In one embodiment, the IC design layout can include a first feature placed on a first...
|
01-Nov-2011 |
| 331 |
US 8051399 B2
patent document
|
IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysis
An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which an output of a cell is expected to switch, and performing timing...
|
01-Nov-2011 |
| 332 |
US 8049312 B2
patent document
|
Semiconductor device package and method of assembly thereof
A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip...
|
01-Nov-2011 |
| 333 |
US 8048750 B2
patent document
|
Method to enhance channel stress in CMOS processes
The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an...
|
01-Nov-2011 |
| 334 |
US 8049465 B2
patent document
|
Systems, methods and circuits for determining micro-short
Various systems and methods for determining micro-shorts are disclosed. For example, some embodiments of the present invention provide battery systems including a determination of potential micro-shorts based...
|
01-Nov-2011 |
| 335 |
US 8049654 B2
patent document
|
Digital trimming of SAR ADCs
Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive...
|
01-Nov-2011 |
| 336 |
US 8050254 B2
patent document
|
IC reconstructing lost speech packets from secondary stage partial data
A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the network interface. The at least one...
|
01-Nov-2011 |
| 337 |
US 8050641 B2
patent document
|
Limiting the power consumption of a wireless electronic system
In at least some disclosed embodiments, a wireless electronic system includes a decoder module coupled to a processor. The decoder module is configured to send a signal to the processor based on a less than...
|
01-Nov-2011 |
| 338 |
US 8051398 B2
patent document
|
Test method and system for characterizing and/or refining an IC design cycle
Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical paths within the integrated circuit design are...
|
01-Nov-2011 |
| 339 |
US 8047660 B2
patent document
|
Projection system and method including spatial light modulator and compact diffractive optics
A method and apparatus for a projection display system includes a spatial light modulator and a volume illumination hologram. The spatial light modulator comprises a digital micromirror device, and the...
|
01-Nov-2011 |
| 340 |
US 8050657 B2
patent document
|
Tamper resistant circuitry and portable electronic devices
A portable electronic device. Tamper-resistant circuitry for inclusion in an electronic device. The tamper-resistant circuitry comprises wireless receiving circuitry operable to receive an incoming...
|
01-Nov-2011 |
| 341 |
US 8050903 B1
patent document
|
Apparatus and method for checkpointing simulation data in a simulator
Apparatus for storing all logic simulation signal values generated by a logic simulator during a simulation run is provided. The apparatus includes a runtime array for storing a plurality of signal values for...
|
01-Nov-2011 |
| 342 |
US 8051313 B2
patent document
|
Apparatus, system and method of power state control
An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the...
|
01-Nov-2011 |
| 343 |
US 8049119 B2
patent document
|
Integrated circuit package having integrated faraday shield
A packaged integrated circuit (IC) (100) includes a first substrate (110) comprising a first plurality of layers and a first circuit coupling features (112) at an upper surface of the first substrate (110), the...
|
01-Nov-2011 |
| 344 |
US 8049254 B2
patent document
|
Semiconductor device with gate-undercutting recessed region
A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface...
|
01-Nov-2011 |
| 345 |
US 8050148 B2
patent document
|
Flash time stamp apparatus
One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the clock input, with a plurality of delay elements inside...
|
01-Nov-2011 |
| 346 |
US 2011/0260708 A1
patent application
|
Bandgap reference circuit and method
A circuit for generating a band gap reference voltage (VREF) includes circuitry (I3×7) for supplying a first current to a first conductor (NODE1) and a second current to a second conductor (NODE2). The first...
|
27-Oct-2011 |
| 347 |
US 2011/0260766 A1
patent application
|
Digital suppression of spikes on an i2c bus
An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I2C) bus is provided. The apparatus comprises a serial data (SDA) filter, a serial clock (SCL) filter, I2C interface logic, and...
|
27-Oct-2011 |
| 348 |
US 2011/0260899 A1
patent application
|
INL correction circuitry and method for SAR ADC
INL error in a SAR ADC (10) is reduced by providing correction capacitors (11B) each having a first terminal connected to a conductor (13) which is also connected to one terminal of the capacitors of a CDAC...
|
27-Oct-2011 |
| 349 |
US 2011/0261328 A1
patent application
|
Apparatus and Method for Reducing Speckle in Display of Images
An apparatus and method of reducing speckle in projection of images is provided that includes the elements or features of producing a first image and displacing the first image to produce a second image that...
|
27-Oct-2011 |
| 350 |
US 2011/0261719 A1
patent application
|
Systems, processes and integrated circuits for improved packet scheduling of media over packet
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline...
|
27-Oct-2011 |
| 351 |
US 2011/0264970 A1
patent application
|
Low power testing of very large circuits
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan...
|
27-Oct-2011 |
| 352 |
US 2011/0261629 A1
patent application
|
Reduced Power Consumption in Retain-Till-Accessed Static Memories
Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells formed of array transistors;...
|
27-Oct-2011 |
| 353 |
US 2011/0261632 A1
patent application
|
Combined Write Assist and Retain-Till-Accessed Memory Array Bias
Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of...
|
27-Oct-2011 |
| 354 |
US 2011/0263051 A1
patent application
|
Interleaf for leadframe identification
A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The...
|
27-Oct-2011 |
| 355 |
US 2011/0261609 A1
patent application
|
Retain-Till-Accessed Power Saving Mode in High-Performance Static Memories
Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells of the 8-T or 10-T type, with...
|
27-Oct-2011 |
| 356 |
US 8044649 B2
patent document
|
Dual mode regulation loop for switch mode power converter
The invention relates to a DC-DC converter, which includes a power stage driven by a pulse width modulator, a first error amplifier with a first input coupled to a first reference voltage source and a second...
|
25-Oct-2011 |
| 357 |
US 8045576 B2
patent document
|
Methods and apparatus to manage power consumption in wireless local area network devices
Methods and apparatus to manage power consumption in wireless devices are disclosed. A disclosed example apparatus comprises performing a first received signal strength indicator (RSSI) scan to determine a...
|
25-Oct-2011 |
| 358 |
US 8045632 B2
patent document
|
Systems and methods for dual-carrier modulation encoding and decoding
Systems and methods for dual-carrier modulation (DCM) encoding and decoding for communication systems. Some embodiments comprise a DCM encoder for applying a pre-transmission function to at least one 16-QAM...
|
25-Oct-2011 |
| 359 |
US 8043921 B2
patent document
|
Nitride removal while protecting semiconductor surfaces for forming shallow junctions
A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD)...
|
25-Oct-2011 |
| 360 |
US 8043947 B2
patent document
|
Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate
A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal...
|
25-Oct-2011 |
| 361 |
US 8044610 B2
patent document
|
LED driver with adaptive algorithm for storage capacitor pre-charge
A method is provided for driving a plurality of light emitters in a plurality of output paths with each output path including at least one light emitter. The method includes the steps of applying a supply...
|
25-Oct-2011 |
| 362 |
US 8045662 B2
patent document
|
Binary ripple counter sampling with adjustable delays
The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with adjustable delay elements that permit accurate...
|
25-Oct-2011 |
| 363 |
US 8045941 B2
patent document
|
Methods and apparatus to implement receiver linearity enhancement
Methods and apparatus to implement receiver linearity enhancement are described. One example method includes controlling receiver gain by determining a level of a received signal that is to be provided to a...
|
25-Oct-2011 |
| 364 |
US 8046748 B2
patent document
|
Method and system to emulate an M-bit instruction set
A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first...
|
25-Oct-2011 |
| 365 |
US 8042248 B2
patent document
|
Low cost window production for hermetically sealed optical packages
Disclosed embodiments demonstrate batch processing methods for producing optical windows for micro-devices. The windows protect the active elements of the micro-device from contaminants, while allowing light to...
|
25-Oct-2011 |
| 366 |
US 8043973 B2
patent document
|
Mask overhang reduction or elimination after substrate etch
A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the...
|
25-Oct-2011 |
| 367 |
US 8044712 B2
patent document
|
Circuit and method for improved frequency resolution of wide-bandwidth digitally programmable RC active filters
An active RC filter (20) includes a first resistive element (23) and a first capacitor array (10/50) which co-acts with the first resistive element (23) to determine a bandwidth characteristic of the...
|
25-Oct-2011 |
| 368 |
US 8044611 B2
patent document
|
LED control device
An LED controller is provided that can easily control light-on testing of LEDs. A super voltage can be added to a signal including a low voltage and a high voltage. When the super voltage is not detected, LED...
|
25-Oct-2011 |
| 369 |
US 8045317 B2
patent document
|
Current limited voltage source with wide input current range
An integrated electronic device includes circuitry for providing a regulated output supply voltage level at an output node from an adjustable current. The circuitry includes an adjustable current source for...
|
25-Oct-2011 |
| 370 |
US 8045922 B2
patent document
|
Apparatus for and method of bluetooth and wireless local area network coexistence using a single antenna in a collocated device
A novel and useful apparatus for and method of providing a mechanism for achieving coexistence between a Bluetooth system and WLAN system collocated in the same communications device such as a mobile terminal....
|
25-Oct-2011 |
| 371 |
US 8046228 B2
patent document
|
Voice activated hypermedia systems using grammatical metadata
This is a voice activated Hypermedia system using grammatical metadata, the system comprising: a speech user agent; a browsing module; and an information resource. The system may include: embedded intelligence...
|
25-Oct-2011 |
| 372 |
US 8043545 B2
patent document
|
Methods and apparatus to evenly clamp semiconductor substrates
Methods and apparatus to evenly clamp semiconductor substrates in a transfer mold process are disclosed. A disclosed split mold base includes a first plate having a first surface, a second plate having a second...
|
25-Oct-2011 |
| 373 |
US 8046199 B2
patent document
|
System and method for computing parameters for a digital predistorter
Digital predistortion system, methods and circuitry for adapting a predistortion system linearizing a non-linear element. The system is a multiply partitioned architecture that addresses long or “memory”...
|
25-Oct-2011 |
| 374 |
US 8046650 B2
patent document
|
TAP with control circuitry connected to device address port
The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each...
|
25-Oct-2011 |
| 375 |
US 8044644 B2
patent document
|
Symmetric sample and hold over-current sensing method and apparatus
An over-current condition is detected in a synchronous DC-DC converter by sampling and holding a measured load current value. The load current is sampled while a low-side transistor is ON and then held when the...
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25-Oct-2011 |
| 376 |
US 8044646 B2
patent document
|
Voltage regulator with quasi floating gate pass element
Various apparatuses, methods and systems for a voltage regulator are disclosed herein. For example, some embodiments provide an apparatus for regulating a voltage including an N-channel transistor that is...
|
25-Oct-2011 |
| 377 |
US 8045670 B2
patent document
|
Interpolative all-digital phase locked loop
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a...
|
25-Oct-2011 |
| 378 |
US 8045661 B2
patent document
|
System and method for blind identification of multichannel finite impulse response filters using an iterative structured total least-squares technique
A system for, and method of, blind identification of multichannel finite impulse response filters. In one embodiment, the system includes: (1) a decomposition generator configured to construct, from noisy...
|
25-Oct-2011 |
| 379 |
US 8046651 B2
patent document
|
Compare circuit receiving scan register and inverted clock flip-flop data
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The...
|
25-Oct-2011 |
| 380 |
US 8044495 B2
patent document
|
Metallic leadframes having laser-treated surfaces for improved adhesion to polymeric compounds
A leadframe for the assembly of a semiconductor chip has regions (112) with an original smooth surface of glossy appearance and regions (113, 114, 210) of a frosty appearance with rough surface contours. The...
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25-Oct-2011 |
| 381 |
US 8046649 B2
patent document
|
Scan circuits formed peripheral of core circuits with control leads
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an...
|
25-Oct-2011 |
| 382 |
US 8044741 B2
patent document
|
Systems and methods for reducing flicker noise in an oscillator
Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide LC tank circuits having an inductance and a capacitance. In...
|
25-Oct-2011 |
| 383 |
US 8045836 B2
patent document
|
System and method for recording high frame rate video, replaying slow-motion and replaying normal speed with audio-video synchronization
A method to record high frame rate video, compatible with existing industry standards, that permits selecting either slow-motion playback or true speed playback with synchronized audio.
|
25-Oct-2011 |
| 384 |
US 2011/0254150 A1
patent application
|
Method of Manufacturing a Semiconductor Device
The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the...
|
20-Oct-2011 |
| 385 |
US 2011/0256729 A1
patent application
|
Showerhead for CVD Depositions
A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a...
|
20-Oct-2011 |
| 386 |
US 2011/0255136 A1
patent application
|
Apparatus and method for transmitting data in a multi-channel system
Conventional analog front ends or AFEs for scanners are implemented using multiple integrated circuits or ICs. As a result, there is typically a problem of skew (due at least in part to manufacturing process...
|
20-Oct-2011 |
| 387 |
US 2011/0255433 A1
patent application
|
Robust packet detection, symbol timing, channel length estimation and channel response estimation for wireless systems
A method in accordance with an embodiment of the invention includes producing a first signal match indication based on at least one match indication indicative of a match between at least one signal received in...
|
20-Oct-2011 |
| 388 |
US 2011/0256687 A1
patent application
|
Method for Fabricating Through Substrate Microchannels
A method of forming large microchannels in an integrated circuit by etching an enclosed trench into the substrate and later thinning the backside to expose the bottom of the trenches and to remove the material...
|
20-Oct-2011 |
| 389 |
US 2011/0257943 A1
patent application
|
Node-based transient acceleration method for simulating circuits with latency
When modeling a circuit, transient analysis is an important part of the analysis. However, for transient analyses, device model evaluating can consume a considerable amount of time, when using conventional...
|
20-Oct-2011 |
| 390 |
US 2011/0253999 A1
patent application
|
Semiconductor wafer having scribe line test modules including matching portions from subcircuits on active die
A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at...
|
20-Oct-2011 |
| 391 |
US 2011/0254881 A1
patent application
|
System and Method for Dynamically Altering a Color Gamut
System and method for dynamically altering a color gamut used in projection display systems. An embodiment comprises determining a dim color from colors used in representing an image, adjusting the dim color to...
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20-Oct-2011 |
| 392 |
US 2011/0255453 A1
patent application
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System and method for scrambling and time-hopping
A system and method for scrambling and time-hopping in an ultra-wideband wireless network. In one embodiment, a wireless device includes a symbol mapper and a dynamic chip scrambler. The dynamic chip scrambler...
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20-Oct-2011 |
| 393 |
US 2011/0258506 A1
patent application
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Reduced signaling interface method & apparatus
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins...
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20-Oct-2011 |
| 394 |
US 2011/0258500 A1
patent application
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Adapting scan architectures for low power operation
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture....
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20-Oct-2011 |
| 395 |
US 2011/0254603 A1
patent application
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Phase interpolator and a delay circuit for the phase interpolator
Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase...
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20-Oct-2011 |
| 396 |
US 2011/0254729 A1
patent application
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Cross coupled positioning engine (Pe) architecture for sensor integration in global navigation satellite system (Gnss)
Embodiments of the disclosure provide a cross coupled position engine architecture for sensor integration in a Global Navigation Satellite System. In one embodiment, a data processing engine for processing...
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20-Oct-2011 |
| 397 |
US 2011/0255557 A1
patent application
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Coexistence of Prime, S-FSK and G3 Devices in Powerline Communications
Communication devices, such as base nodes and modems, that comply with two or more different standards operate on a shared communication channel. To avoid mutual interference, a base node operating under a...
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20-Oct-2011 |
| 398 |
US 2011/0258502 A1
patent application
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Wafer scale testing using a 2 signal jtag interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on...
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20-Oct-2011 |
| 399 |
US 8040986 B2
patent document
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Frequency-domain subchannel transmit antenna selection and power pouring for multi-antenna transmission
A system comprises a wireless device that communicates across a spectrum having a plurality of sub-channels. The wireless device comprises a plurality of antennas through which the wireless device communicates...
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18-Oct-2011 |
| 400 |
US 8041998 B2
patent document
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Data processor decoding trace-worthy event collision matrix from pipelined processor
A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data...
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18-Oct-2011 |