Texas Instruments

A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is...

A process of forming a semiconductor process fabricated device which contains a trench, hole or gap filled with a conformally deposited material is disclosed. A sacrificial planarizing layer is formed on the...

An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to...

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional...

An embodiment of the invention provides a method of reducing surge current in an LLC converter. The LLC converter comprises a switching circuit having a first switch and a second switch, a resonant circuit, and...

A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first...

An electronic device is provided for controlling a current. The electronic device includes a first MOS transistor coupled with a gate to a common gate node, with a source to ground and with a drain to a pin so...

Performing digital predistortion (DPD) for widely spaced narrowband signals, such as the signal used in multi-carrier GSM, can be very difficult. Here, a system is provided the performs DPD for widely spaced...

A recursive method for computing numerical values for mathematical functions includes providing a recursive Taylor series representation of a mathematical function f(x) of a variable x evaluated around a given...

A multi-chambered system for electroplating metal layers on a semiconductor substrate. The system comprises a fluid reservoir having at least a first chamber and a second chamber. A cathode is located in the...

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on...

Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is...

Exemplary embodiments provide a method for fabricating an integrated circuit (IC) device with reduced streak defects. In one embodiment, the IC device structure can be formed having a first pad oxide-based...

A sequence of cyclic redundancy check syndromes can be produced based on a received sequence of sets of parallel data wherein different ones of the sets can have respectively different parallel data widths....

A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the...

A wireless communication system (40). The system comprises transmitter circuitry (42) comprising encoder circuitry (44) for receiving a plurality of symbols (Si). The system further comprises a plurality of...

An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch...

An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first...

A circuit for providing a write current having a programmably adjustable duty cycle in a hard disk drive write channel has a differential pair gain circuit for receiving a data input signal and generating a...

A wavelength conversion device comprising a plurality of regions. Each region for absorbing radiant energy and emitting light having a characteristic dependent upon which region of the device emits the light.

A variable gain amplifier may include a master amplifier that may be configured to generate a first current and a diode coupled with the master amplifier so that the first current passes through the diode...

In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets...

A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first dimension of a first length and a second dimension...

An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access...

Because of variations in open loop gain and bandwidth in successive approximate register (SAR) analog-to-digital converters (ADCs), designing amplifiers with the desired characteristics is difficult. Here, a...

A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper...

In a method and apparatus for saving power in a device coupled to a bus, the device is placed to operate in a power saving mode by powering off a selective portion of the device including a device clock. If...

The invention provides semiconductor chip packages, tools, and methods for preventing and for correcting leadfinger deformation caused during wirebonding in semiconductor chip package manufacturing. Disclosed...

An over current protection device is described. It includes a plurality of input channels for receiving an input signal; a plurality of low pass filters coupled to a first group of the plurality of input...

Traditionally, switching amplifiers (i.e., class-D and class-G) with negative supply rails had issues with direct current (DC) power loss, included large external capacitors, had a comparative reduction in...

An IC die includes active circuitry and I/O nodes tied together in first net and at least a second net. A first die pad and a second die pad adjacent thereto are coupled to the first and second net,...

A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The electro-optical circuit has an active region that is...

A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245)...

A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan...

A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to...

Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added...

An integrated circuit package includes a die, a bump, an underbump metallization layer formed between the bump and the die, a portion of the underbump metallization layer under the bump having a first radius,...

Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads...

A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the...

An electronic package 100 comprising a semiconductor device 105, a heat spreader layer 110, and a thermal interface material layer 115 located between the semiconductor device and the heat spreader layer. The...

A DC-DC converter has high-side power and low-side power transistors connected in series between supply terminals, an inductor connected between the power transistors and an output terminal. A comparator...

A chemical mechanical polishing pad and method for chemical-mechanical polishing is provided, wherein the polishing pad has a plurality of first mesas and one or more second mesas defined on a surface thereof....

Embodiments of the invention apply block spreading to transmitted signals to increase the number orthogonally multiplexed signals. The principle of the disclosed invention can be applied to reference signals,...

One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region...

An electrical device comprising an electronic component mounted to a surface of a printed circuit board, a ground connection on said surface, and electromagnetic interference (EMI) shielding. The EMI shielding...

The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and...

A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the...

The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses...

In bipolar CMOS or BiCMOS process technologies, drivers (such as mixed mode or hybrid mode drivers) using both bipolar and CMOS transistors (i.e., field effect transistors or FETs) may have undesirable...