Texas Instruments

An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports, where the memory base cell includes a first storage...

A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel...

An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I2C) or I2C compatible bus. The IC is further configured to receive an address through the I2C bus and store the...

A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die...

A navigation system determines its usage mode. In some embodiments, a method comprises determining a usage mode of a navigation system based on at least one of an acceleration indicator, a speed indicator, and...

A converter has a single inductor with a first terminal connectable to a first terminal of the supply input through a first power transistor and a second terminal connectable to a second terminal of the supply...

A system (500) removes wafer edge residue from a target wafer (508). A wafer holding mechanism (502) holds and rotates the target wafer (508). A residue remover mechanism (504) mechanically interacts or abrades...

A current canceling CMOS variable gain amplifier includes a first leg and a second leg. The first leg has a first input line, a first output line, a first ON transistor, a first control transistor and a first...

The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is...

Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan...

A deformable hinge for use in microelectromechanical devices comprises a protection layer that is electrically conductive. The protection layer is on top of another hinge layer; and is more resistive than the...

Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent...

Methods for power factor correction (PFC) and for reducing conduction losses and switching losses in a power converter as well as the power converter and phase management circuitry for the power converter. The...

The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without leakage. A second semiconductor layer (12, 16) of...

An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain...

With high speed, high resolution time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches between the various ADC branches can pose a significant problem. Previously, though, no adequate...

Conventional retimers generally consume too much power, are too noisy, and are too large. Additionally, phase noise and jitter are generally a function of retiming. As a result, a retimer is provided with a...

Today, 100BaseT is commonly used in industrial Ethernet application. As a result of being in such an environment, Ethernet cables are subject to abuse, which can result in costly failures and repairs. Here, a...

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture....

One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node and a second control node to the other of the first...

A system comprises a spatial light modulator comprising a plurality of modulation elements, the spatial light modulator operable to receive an optical signal comprising one or more optical channels, wherein the...

A processor in a digital system executes instructions in an instruction execution pipeline. The processor detects a pipeline protection directive while executing instructions and sets a pipeline protection mode...

A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low stress sacrificial cap layer 410 having a silicon...

For combining light from different light sources that are spatially apart, an optical system comprises a prism assembly that comprises a totally-internally-surface and a dichroic filter. The...

An integrated electrostatic discharge (ESD) device includes a first ESD structure coupled to a pad terminal of the integrated ESD device and a second ESD structure coupled to a ground terminal of the integrated...

An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a p-type region laterally annularly encircling the...

A master electronic circuit (300) includes a storage (324) representing a wireless collision avoidance networking process (332) involving collision avoidance overhead and combined with a schedulable process...

Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a...

An electronic circuit (2250) for a satellite receiver (100, 2200). The electronic circuit (2250) includes a correlator circuit (2310) operable to supply a data signal including ephemeris data and a subsequent...

A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum...

A controller that shares an interface with several other controllers connected in a scan topology in a target system may be selected by receiving a selection event and a selection sequence containing selection...

A method for driving a light-emitting semiconductor is provided. A supply voltage is converted into a secondary output voltage for supplying the light-emitting semiconductor with an output voltage. A level for...

This invention is power supply protection for complex digital circuits employing an external high voltage supply and an internally generated low voltage core logic supply. Precision analog comparators...

Interlaced-to-progressive conversion with (1) 3-2 pulldown detection, (2) pre-filtering for field motion detection, (3) field motion detection with feedback, (4) field edge detection including direction angle...

A system comprises a circuit configured to execute instructions and output event data corresponding to the execution of the instructions. The system also comprises a monitoring device coupled to the circuit....

A system for managing AC energy harvested from a harvesting device (1) including a coil (4) including switching circuitry (S1-S4) coupled between first (7A) and second (7B) terminals of the coil. The switching...

Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan apparatus having a first boundary scan circuit with a...

An integrated circuit containing an SCRMOS transistor. The SCRMOS transistor has one drain structure with a centralized drain diffused region and distributed SCR terminals, and a second drain structure with...

An integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal. The RESURF region is the same conductivity type as the drift region and is more heavily doped...

In at least some embodiments, a communication device includes a transceiver with Carrier Sensing Multiple Access with Collision Avoidance (CSMA-CA) logic. The CSMA-CA logic provides dynamic randomization...

A system and method for reducing transmission collisions. In one embodiment, a transmitter for communicating of a smart grid power line network includes an arbiter. The arbiter is configured to select a...

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full...

Determining operating context of an executed instruction. At least some of the illustrative embodiments are a computer-readable medium storing a debug-trace program that, when executed by a processor, causes...

A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features corresponding to a...

A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has...

With conventional redrivers used for external Serial Advanced Technology Attachment (eSATA), there is no ability to indicated to a host that an external device (like a hard disk drive) is not present. As a...

An electronic device controlling a frequency modulation index has a frequency modulation index control loop having an input adapted to be connected to a frequency output of a frequency controllable oscillator....

A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to...

Driver circuit for high voltage differential signaling. The circuit includes a first positive driver that generates a first positive transition at a first output in response to an input. The circuit also...

A switched mode power supply has a high side switching transistor coupled between a voltage source and a load for generating the output voltage at the load. A driver circuit drives the high side switching...