| No | Document | Title | Date |
|---|---|---|---|
| 1 |
US 2012/0025890 A1
patent application
|
Circuitry and method for preventing base-emitter junction reverse bias in comparator differential input transistor pair
A differential input circuit (1-1) includes first (Q0) and second (Q1) input transistors having control electrodes coupled to first (Vin+) and second (Vin−) input signals, respectively. A pass transistor (P3)...
|
02-Feb-2012 |
| 2 |
US 2012/0026808 A1
patent application
|
Integrated Circuit With Low Power SRAM
An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is...
|
02-Feb-2012 |
| 3 |
US 2012/0028431 A1
patent application
|
Method for manufacturing a semiconductor device using a nitrogen containing oxide layer
The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate...
|
02-Feb-2012 |
| 4 |
US 2012/0025891 A1
patent application
|
Bipolar transistor anti-saturation clamp using auxiliary bipolar stage, and method
An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of...
|
02-Feb-2012 |
| 5 |
US 2012/0026754 A1
patent application
|
Double phase-shifting full-bridge dc-to-dc converter
A DC-to-DC converter has a leading full-bridge inverter and a lagging full-bridge inverter for receiving a DC input and producing respective AC output voltages. A full-wave rectifier circuit rectifies the AC...
|
02-Feb-2012 |
| 6 |
US 2012/0030447 A1
patent application
|
Process, circuits, devices, and systems for encryption and decryption and other purposes, and processes of making
A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads...
|
02-Feb-2012 |
| 7 |
US 2012/0026213 A1
patent application
|
Illumination source and method therefor
An illumination source and a method therefor. A light source includes a light circuit configured to process light and direct light, and a lighting element optically coupled to the light circuit to provide...
|
02-Feb-2012 |
| 8 |
US 2012/0026367 A1
patent application
|
System and method for maintaining maximum input rate while up-scaling an image vertically
An example embodiment provides a resizer in an image processing system. The resizer includes a receiving module that receives pixel data representative of an image. A triple line buffer is coupled to the...
|
02-Feb-2012 |
| 9 |
US 2012/0025901 A1
patent application
|
Sensor node voltage clamping circuit and method
A voltage clamping circuit includes a current source having a fixed current source and a variable current source and a variable resistor receiving current from the current source. The variable resistor varies...
|
02-Feb-2012 |
| 10 |
US 2012/0026762 A1
patent application
|
Pre-Bias Control for Switched Mode Power Supplies
An embodiment of the invention provides a method of reducing a drop in voltage on a pre-biased output of a DC-DC step-down switching converter. A high side switch is activated to conduct a first current to the...
|
02-Feb-2012 |
| 11 |
US 2012/0030532 A1
patent application
|
Structures and control processes for efficient generation of different test clocking sequences, controls and other test signals in scan designs with multiple partitions, and devices, systems and processes of making
A scannable integrated circuit (100) including a functional integrated circuit (P1, P2) having scan chains, multiple scan decompressors (120.1, 120.2), each operable to supply scan bits to some of the scan...
|
02-Feb-2012 |
| 12 |
US 2012/0026039 A1
patent application
|
Single rf receiver chain architecture for gps, galileo and glonass navigation systems, and other circuits, systems and processes
A wireless receiver for multiple frequency bands reception includes a single receive radio frequency (RF) circuit (160, 170) having an RF bandpass substantially confined to encompass at least two non-overlapped...
|
02-Feb-2012 |
| 13 |
US 8108641 B2
patent document
|
Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices
A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for...
|
31-Jan-2012 |
| 14 |
US 8107547 B2
patent document
|
Receivers for embedded ACK/NAK in CQI reference signals in wireless networks
Within a wireless network, uplink control information (UCI) transmitted by user equipment is received by a base station. The UCI includes a least two elements, a first set of symbols produced using a first...
|
31-Jan-2012 |
| 15 |
US 8107570 B2
patent document
|
Space time block coded transmit antenna diversity for WCDMA
A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+τj), i=0−N−1) during a first time (T0-T1) from an external source and coupled to receive a...
|
31-Jan-2012 |
| 16 |
US 8107420 B2
patent document
|
Wireless communications system with cycling of unique cell bit sequences in station communications
A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver in a first cell (Cell 1). Each of the plurality...
|
31-Jan-2012 |
| 17 |
US 8108742 B2
patent document
|
Tap control of TCA scan clock and scan enable
The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the...
|
31-Jan-2012 |
| 18 |
US 2012/0019947 A1
patent application
|
Technique for programmable rise time in hard disk drive writer
A write channel for a hard disk drive has a write current with a programmably adjustable rise time, and includes first and second analog write data signal paths having respective resistive nodes. First and...
|
26-Jan-2012 |
| 19 |
US 2012/0020266 A1
patent application
|
Power state and medium access coordination in coexisting wireless networks
Apparatus and method for improving throughput in a wireless device accessing coexisting networks. In one embodiment, a wireless device includes first and second wireless transceivers, a power state controller,...
|
26-Jan-2012 |
| 20 |
US 2012/0023313 A1
patent application
|
Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture
An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first...
|
26-Jan-2012 |
| 21 |
US 2012/0019324 A1
patent application
|
Amplifier With Improved Input Resistance and Controlled Common Mode
An amplifier includes a first pair of transistors (the first pair) that defines a first output, each transistor of the first pair having a gate coupled to a first input terminal; a second pair of transistors...
|
26-Jan-2012 |
| 22 |
US 2012/0023381 A1
patent application
|
Integrated circuit with jtag port, tap linking module, and off-chip tap interface port
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be...
|
26-Jan-2012 |
| 23 |
US 2012/0019263 A1
patent application
|
Precision Measurement of Capacitor Mismatch
Circuitry and methods for measuring capacitive mismatch with improved precision. The capacitors under measurement are connected in series in a voltage divider, with the node common to both capacitors connected...
|
26-Jan-2012 |
| 24 |
US 2012/0018810 A1
patent application
|
Structure And Method For Dual Work Function Metal Gate CMOS With Selective Capping
A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a...
|
26-Jan-2012 |
| 25 |
US 2012/0019918 A1
patent application
|
System and method for reducing visible speckle in a projection visual display system
The disclosure provides an apparatus for reducing speckle in a projection visual display (PVD) system, a method of reducing visible speckle in a PVD system and a PVD system incorporating the method or...
|
26-Jan-2012 |
| 26 |
US 2012/0019280 A1
patent application
|
Integrated circuit having electrically isolatable test circuitry
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is...
|
26-Jan-2012 |
| 27 |
US 8102038 B2
patent document
|
Semiconductor chip attach configuration having improved thermal characteristics
A semiconductor chip 101 with surface 101b free of circuitry assembled on a metal carrier 102 by an attachment layer 103 with thickness 103a. Included in layer 103 are metal bodies 104 and an adhesive polymeric...
|
24-Jan-2012 |
| 28 |
US 8101476 B2
patent document
|
Stress memorization dielectric optimized for NMOS and PMOS
A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is...
|
24-Jan-2012 |
| 29 |
US 8102187 B2
patent document
|
Localized calibration of programmable digital logic cells
An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell...
|
24-Jan-2012 |
| 30 |
US 8102809 B2
patent document
|
Time-sharing of sounding resources
This invention is a method for time-sharing sounding resources. This invention time-shares one sounding source across plural user equipment for different sub-frames. This invention uses different sounding...
|
24-Jan-2012 |
| 31 |
US 2012/0012941 A1
patent application
|
Formation of metal gate electrode using rare earth alloy incorporated into mid gap metal
Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a...
|
19-Jan-2012 |
| 32 |
US 2012/0017067 A1
patent application
|
On-demand predicate registers
In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also...
|
19-Jan-2012 |
| 33 |
US 2012/0012982 A1
patent application
|
Capacitors and methods of forming
Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer...
|
19-Jan-2012 |
| 34 |
US 2012/0014173 A1
patent application
|
Disturb-Free Static Random Access Memory Cell
A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for...
|
19-Jan-2012 |
| 35 |
US 2012/0014243 A1
patent application
|
Allocation and Logical to Physical Mapping of Scheduling Request Indicator Channel in Wireless Networks
A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is transmitted from a NodeB in a cell to UE within the...
|
19-Jan-2012 |
| 36 |
US 2012/0013390 A1
patent application
|
Displayport switch
In versions 1.1a and 1.2 of the DISPLAYPORT™ standard, capacitors are used between a sourcing circuit and a switch for the auxiliary channel. As a result, these capacitors are generally uncharged when the...
|
19-Jan-2012 |
| 37 |
US 2012/0014454 A1
patent application
|
Method and Apparatus for Parallel Context Processing
A method and apparatus for parallel context processing for example for high coding efficient entropy coding in HEVC. The method comprising retrieving syntax element relating to a block of an image, grouping at...
|
19-Jan-2012 |
| 38 |
US 2012/0013003 A1
patent application
|
Bga package with traces for plating pads under the chip
A semiconductor flip-chip ball grid array package with one-metal-layered substrate. The sites of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O...
|
19-Jan-2012 |
| 39 |
US 2012/0014194 A1
patent application
|
Memory Cell with Equalization Write Assist in Solid-State Memory
A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an equalization gate...
|
19-Jan-2012 |
| 40 |
US 2012/0015478 A1
patent application
|
Integrated Circuit Stacked Package Precursors and Stacked Packaged Devices and Systems Therefrom
A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top...
|
19-Jan-2012 |
| 41 |
US 2012/0015479 A1
patent application
|
Semiconductor Package with a Mold Material Encapsulating a Chip and a Portion of a Lead Frame
Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an...
|
19-Jan-2012 |
| 42 |
US 2012/0017129 A1
patent application
|
High speed double data rate jtag interface
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the...
|
19-Jan-2012 |
| 43 |
US 2012/0015483 A1
patent application
|
Semiconductor Device Package and Method of Assembly Thereof
A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip...
|
19-Jan-2012 |
| 44 |
US 8099641 B2
patent document
|
Multiplexer selecting STP clock signal with tap control outputs
Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a...
|
17-Jan-2012 |
| 45 |
US 8097964 B2
patent document
|
IC having TSV arrays with reduced TSV induced stress
An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal...
|
17-Jan-2012 |
| 46 |
US 8098091 B1
patent document
|
Method in the compensation of unlinearities in an amplifier, and uses of the method and the amplifier
In a method and an amplifier for the compensation of unlinearities e.g. of the class D type, wherein an audio signal is pulse-width modulated, e.g. with a carrier wave signal in the form of a triangular signal...
|
17-Jan-2012 |
| 47 |
US 8098745 B2
patent document
|
Random access structure for wireless networks
Apparatus and methods for accessing a wireless telecommunications network by transmitting a random access signal. The random access signal includes a random access preamble signal selected from a set of random...
|
17-Jan-2012 |
| 48 |
US 8099658 B2
patent document
|
Reduced complexity Viterbi decoder
A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a...
|
17-Jan-2012 |
| 49 |
US 8099642 B2
patent document
|
Formatter selectively outputting scan stimulus data from scan response data
The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the...
|
17-Jan-2012 |
| 50 |
US 2012/0009739 A1
patent application
|
Metallic Leadframes Having Laser-Treated Surfaces for Improved Adhesion to Polymeric Compounds
A leadframe for the assembly of a semiconductor chip has regions (112) with an original smooth surface of glossy appearance and regions (113, 114, 210) of a frosty appearance with rough surface contours. The...
|
12-Jan-2012 |
| 51 |
US 2012/0007992 A1
patent application
|
Method and Apparatus for Sub-Picture Based Raster Scanning Coding Order
A method and apparatus for sub-picture based raster scanning coding order. The method includes dividing an image into even sub-pictures, and encoding parallel sub-pictures on multi-cores in raster scanning...
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12-Jan-2012 |
| 52 |
US 2012/0008102 A1
patent application
|
On-Axis Projection Lens with Offset
A method and system of projecting images with high degrees of image offset while limiting the physical offset of the projection lens elements. The methods and systems provided limit the displacement of the...
|
12-Jan-2012 |
| 53 |
US 2012/0011294 A1
patent application
|
System and method for secure authentication of a "Smart" battery by a host
Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In one embodiment, the system for providing a battery...
|
12-Jan-2012 |
| 54 |
US 2012/0011410 A1
patent application
|
Scan test method and apparatus
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The...
|
12-Jan-2012 |
| 55 |
US 2012/0007687 A1
patent application
|
Digital Amplitude Modulation
A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital...
|
12-Jan-2012 |
| 56 |
US 2012/0008691 A1
patent application
|
Method and apparatus for region-based weighted prediction with improved global brightness detection
A method and apparatus for determining a region-based weighted prediction with improved global brightness detection. The method includes applying a global brightness change detection methods by computing the...
|
12-Jan-2012 |
| 57 |
US 2012/0008718 A1
patent application
|
Wireless Precoding Methods
Various wireless precoding systems and methods are presented. In some embodiments, a wireless transmitter comprises an antenna precoding block, a transform block, and multiple transmit antennas. The antenna...
|
12-Jan-2012 |
| 58 |
US 2012/0007622 A1
patent application
|
Ip core design supporting user-added scan register option
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an...
|
12-Jan-2012 |
| 59 |
US 2012/0007954 A1
patent application
|
Method and apparatus for a disparity-based improvement of stereo camera calibration
A method and apparatus for camera calibration. The method is for disparity estimation of the camera calibration and includes collecting statistical information from at least one disparity image, inferring...
|
12-Jan-2012 |
| 60 |
US 2012/0008768 A1
patent application
|
Mode control engine (Mce) for confidentiality and other modes, circuits and processes
An electronic data processing module (600) includes a context storage (640), cryptographic cores (615.i) adapted for acceleration of respective different types of encryption and decryption, and a mode control...
|
12-Jan-2012 |
| 61 |
US 2012/0011351 A1
patent application
|
Security Processing Engines, Circuits and Systems and Adaptive Processes and Other Processes
An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane...
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12-Jan-2012 |
| 62 |
US 2012/0008187 A1
patent application
|
System and Method for Operating Light Processing Electronic Devices
A system and method for operating an electronic device used in light processing. A method comprises altering a spatial relationship between a spatial light modulator (SLM) and a light incident on the SLM,...
|
12-Jan-2012 |
| 63 |
US 2012/0011404 A1
patent application
|
Method and system of a processor-agnostic encoded debug-architecture in a pipelined environment
A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data...
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12-Jan-2012 |
| 64 |
US 2012/0008645 A1
patent application
|
Systems, processes and integrated circuits for rate and/Or diversity adaptation for packet communications
A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the network interface. The at least one...
|
12-Jan-2012 |
| 65 |
US 2012/0008710 A1
patent application
|
Mapping Schemes for Secondary Synchronization Signal Scrambling
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to...
|
12-Jan-2012 |
| 66 |
US 2012/0011412 A1
patent application
|
Addressable test access port method and apparatus
The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each...
|
12-Jan-2012 |
| 67 |
US 2012/0011478 A1
patent application
|
Merging sub-resolution assist features of a photolithographic mask
Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second sub-resolution...
|
12-Jan-2012 |
| 68 |
US 8093115 B2
patent document
|
Tuning of SOI substrate doping
A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate...
|
10-Jan-2012 |
| 69 |
US 8094765 B2
patent document
|
Clock and mode signals controlling data communication in three states
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have...
|
10-Jan-2012 |
| 70 |
US 8093688 B2
patent document
|
Device comprising an ohmic via contact, and method of fabricating thereof
Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a conductive barrier layer over the metal layer,...
|
10-Jan-2012 |
| 71 |
US 8095584 B2
patent document
|
Random number generator using jitter sampled RF carrier
A random number generator generates a string of random bits from a received RF signal source. A sample-and-hold circuit is coupled to the received RF signal source. The RF signal is sampled by a jittered clock...
|
10-Jan-2012 |
| 72 |
US 8095838 B2
patent document
|
Transitioning through idle 1, 2 and sequence 1 machine states
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the...
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10-Jan-2012 |
| 73 |
US 8094050 B2
patent document
|
Bandwidth mismatch estimation in time-interleaved analog-to-digital converters
With high speed, high resolution time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches between the various ADC branches can pose a significant problem. Previously, though, no adequate...
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10-Jan-2012 |
| 74 |
US 8094234 B2
patent document
|
System and method for multistage frame rate conversion
System and method for multistage frame rate conversion. A method comprises receiving an incoming frame at a first frame rate, and determining whether a fault condition exists. The method also includes if the...
|
10-Jan-2012 |
| 75 |
US 8093070 B2
patent document
|
Method for leakage reduction in fabrication of high-density FRAM arrays
A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises...
|
10-Jan-2012 |
| 76 |
US 8093878 B2
patent document
|
Switching power supply device
A switching power supply device for a ripple control system that can obtain the ripple component with the necessary amplitude without using discrete elements. On capacitor Ci of CR integrator 11, a voltage is...
|
10-Jan-2012 |
| 77 |
US 8094638 B2
patent document
|
Adaptive selection of transmission parameters for reference signals
An embodiment of the present invention uses estimates of delay spreads of transmissions from user equipments (UEs) to a NodeB to determine a set of transmission parameters for the UEs reference signals. In an...
|
10-Jan-2012 |
| 78 |
US 8095840 B2
patent document
|
Serial scan chain in a star configuration
A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan...
|
10-Jan-2012 |
| 79 |
US 8094352 B2
patent document
|
Mirror assembly with recessed mirror
A mirror device and a method for manufacturing the mirror device are presented. The mirror device includes a mirror formed from a first substrate and a hinge/support structure formed from a second substrate....
|
10-Jan-2012 |
| 80 |
US 8093622 B2
patent document
|
Semiconductor device and its driving method
A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type...
|
10-Jan-2012 |
| 81 |
US 8093716 B2
patent document
|
Contact fuse which does not touch a metal layer
The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced...
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10-Jan-2012 |
| 82 |
US 8093925 B2
patent document
|
Current driver circuit
An integrated regulated current drive circuit for driving a squib of an inflatable airbag has a current sense resistor connected in series with a load, and a reference resistor connected in series with a...
|
10-Jan-2012 |
| 83 |
US 8093941 B2
patent document
|
Systems and devices for dynamically scaled charge pumping
Systems and devices for dynamically scaled charge pumping are presented. Example embodiments of the disclosed systems of dynamically scaled charge pumping enable regulation of the output voltage at a particular...
|
10-Jan-2012 |
| 84 |
US 8095839 B2
patent document
|
Position independent testing of circuits
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs....
|
10-Jan-2012 |
| 85 |
US 2012/0002471 A1
patent application
|
Memory Bit Redundant Vias
An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are...
|
05-Jan-2012 |
| 86 |
US 2012/0002729 A1
patent application
|
Method and apparatus for low cost coefficient-suppression for video compression
A method for video compression and a video encoder. The method for video compression includes finding a coefficient relating to inter-coded block with a biggest absolute value, determining the number of...
|
05-Jan-2012 |
| 87 |
US 2012/0005546 A1
patent application
|
Interconnections for plural and hierarchical p1500 test wrappers
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test...
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05-Jan-2012 |
| 88 |
US 2012/0005400 A1
patent application
|
Dual In Line Memory Module with Multiple Memory Interfaces
A memory module such as a DIMM includes two separate memories with corresponding data, address and control interfaces. Each separate memory core includes plural memory banks for corresponding portions of the...
|
05-Jan-2012 |
| 89 |
US 2012/0002714 A1
patent application
|
Communication on a Pilot Wire
Systems and methods are disclosed for communicating on a pilot wire between Electric Vehicle Service Equipment (EVSE) and an Electric Vehicle (EV). The EVSE and EV exchange a Pulse Width Modulation (PWM) signal...
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05-Jan-2012 |
| 90 |
US 2012/0001336 A1
patent application
|
Corrosion-resistant copper-to-aluminum bonds
A connection formed by a copper wire (112) alloyed with a noble metal in a first concentration bonded to a terminal pad (101) of a semiconductor chip; the end of the wire being covered with a zone (302)...
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05-Jan-2012 |
| 91 |
US 8088664 B2
patent document
|
Method of manufacturing integrated deep and shallow trench isolation structures
A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is...
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03-Jan-2012 |
| 92 |
US 2011/0316740 A1
patent application
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Reacquiring Satellite Signals Quickly
Embodiments of the invention provide a method of reacquiring satellite signals quickly. A pseudorange of at least one satellite is estimated. A user's position is also estimated. Then a signal from at one or...
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29-Dec-2011 |
| 93 |
US 2011/0316505 A1
patent application
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Output Buffer With Improved Output Signal Quality
An output buffer receives an input signal and generates an output signal at an output node. The output buffer contains a driver circuit. The driver circuit includes two pairs of cascoded transistors connected...
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29-Dec-2011 |
| 94 |
US 2011/0317762 A1
patent application
|
Video encoder and packetizer with improved bandwidth utilization
Techniques for managing a video encoding pipeline are disclosed herein. In one embodiment, a video encoder includes a multi-stage encoding pipeline. The pipeline includes an entropy coding engine and a...
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29-Dec-2011 |
| 95 |
US 2011/0317786 A1
patent application
|
System and Method for Estimating a Transmit Channel Response and/or a Feedback Channel Response Using Frequency Shifting
Systems and methods for identifying a transmission channel response and a feedback channel response from a plurality of composite system responses are disclosed. A plurality of shifted feedback signals are...
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29-Dec-2011 |
| 96 |
US 2011/0320850 A1
patent application
|
Offline at start up of a powered on device
A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the...
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29-Dec-2011 |
| 97 |
US 2011/0316089 A1
patent application
|
Semiconductor device with gate-undercutting recessed region
A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface...
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29-Dec-2011 |
| 98 |
US 2011/0316621 A1
patent application
|
Low input bias current chopping switch circuit and method
A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a...
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29-Dec-2011 |
| 99 |
US 2011/0317702 A1
patent application
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Two-Hop Star Network Topology Extension
Relayed nodes communicate with a target hub using a relaying node in a two-hop star network. The relayed nodes transmit a first encapsulating frame having a payload that comprises an encapsulated frame. The...
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29-Dec-2011 |
| 100 |
US 2011/0317719 A1
patent application
|
Data link layer headers
A system for communicating protocol layer processing information is disclosed herein. A transmitter includes a protocol layer header generator that generators a header for a first protocol data unit. The header...
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29-Dec-2011 |